 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| t1mx28 ds1 mapper 28-channel microprocessor interface test access port interface for boundary scan line transceiver alarm/select interface (x 28) system clocks ds1 dual rail/ nrz data & clocks (x 28) telecom bus interface (x 2) txc-04228 line side system side +3.3v line transceiver common control interface add bus drop bus 21 13 3 4 4 2 3 5 (x 4) the t1mx28 ? is a 28-channel byte-synchronous and asyn- chronous ds1 mapper. four field-proven ds1mx7 ds1 mapper chips are interconnected in a single compact pack- age to permit higher application board densities. both sonet and sdh mappings are provided per bellcore gr- 253-core (vt1.5) and itu g.707 3-96. a single-dual add/ drop telecom bus is provided that can operate at either 6.48 or 19.44 mhz, which is compatible with other transwitch devices. vt1.5/tu-11 pointer tracking and overhead extrac- tion/processing with full error and alarm control is provided. vt1.5/tu-11 pointer calculation and overhead assembly is also provided. alarm and error mappings from drop to add and sonet/sdh to/from ds1 are provided. jitter perfor- mance is achieved with a fully digital threshold modulator and dpll that meets gr-253-core mtie requirements without external de-jitter buffers. for the ds1 line, ami, b8zs and nrz line codes are supported with full alarm detection and generation per ansi t1.231-1997. each channel is independently programmable for mixed service applications. access to status and control bits is provided via an intel/ motorola-compatible microprocessor interface. diagnostic, test, and maintenance functions are provided, including boundary scan, prbs generator/analyzer and loopbacks. ? twenty-eight independent 1.544 mbit/s ds1 mappers single/dual byte-parallel telecom bus @ 6.48 mhz (28 slots) or 19.44 mhz (84 slots) floating vt1.5 byte-synchronous mapping with signaling only for use with or without a slip buffer asynchronous mapping for ds1 sonet mapping (vt1.5) or sdh mapping (vc-4/au-3/tu-11) ami or b8zs codec for ds1s, or nrz serial i/o for control of ds1 line interface transceivers or framers telecom bus and ds1 loopbacks with integral prbs generator and analyzer vt1.5/tu-11 pointer tracking and generation vt1.5/tu-11 overhead processing and insertion one-second latched performance registers and counters ds1 alarm detection and generation internal ring port for use as a dual bus 14-channel mapper gapped line clock option for internet applications without need for a framer intel/motorola-compatible microprocessor interface 3-bit rdi support boundary scan capability (ieee 1149.1) single +3.3 v, 5 % power supply 456-lead plastic ball grid array package (35 x 35 mm) sonet/sdh terminal or add/drop multiplexers sup- porting both asynchronous and byte-synchronous modes unidirectional or bidirectional ring applications sonet remote digital terminal equipment sonet cpe equipment requiring access to ds0s sonet/sdh test equipment internet access equipment t1mx28 device ds1 mapper 28-channel txc-04228 document number: preliminary txc-04228-mb ed. 4, september 2001 u.s. patents no. 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,507; 5,297,180; 5,528,598; 5,535,218 u.s. and/or foreign patents issued or pending copyright ? 2001 transwitch corporation t1mx28 is a trademark of transwitch corporation transwitch and txc are registered trademarks of transwitch corporation data sheet preliminary information documents contain information on products in the sampling, pre-production or early production phases of the product life cycle. characteristic data and other specifications are subject to change. contact transwitch applications engineering for current information on this product. proprietary transwitch corporation information for use solely by its customers applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
- 2 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers table of contents section page list of figures ............................................................................................................... ..................... 3 features ...................................................................................................................... ...................... 4 features that are independently selectable for each of the mappers ....................................... 4 features that are only selectable for the twenty-eight mappers as a group ........................... 7 block diagram ................................................................................................................. .................. 9 block diagram description ..................................................................................................... ......... 10 lead diagram .................................................................................................................. ................ 15 lead descriptions ............................................................................................................. ............... 16 absolute maximum ratings and environmental limitations ........................................................... 29 thermal characteristics ....................................................................................................... ........... 29 power requirements ............................................................................................................ ........... 29 input, output and input/output parameters .................................................................................... 3 0 timing characteristics ........................................................................................................ ............. 33 operation ..................................................................................................................... .................... 49 general mapper application overview ..................................................................................... 49 line interface selection ...................................................................................................... ...... 49 asynchronous operation with the line interface .............................................................. 50 byte-synchronous operation with the line interface ........................................................ 52 receive data and signaling highway operation .............................................................. 52 transmit data and signaling highway operation ............................................................. 55 the synchronizer, mapper and overhead generator ....................................................... 57 pointer generation and telecom bus slot selection ........................................................ 59 vt/tu pointer tracking and telecom bus slot selection ................................................ 63 the demapper .................................................................................................................. 66 desynchronization and pointer leak rate calculations ................................................... 68 jitter measurements ........................................................................................................... ...... 71 microprocessor interface and common control/status i/o ..................................................... 77 serial port control interface ................................................................................................. .... 81 t1mx28 channel testing using the prbs generator and analyzer ................................ 81 telecom bus interface ......................................................................................................... .... 83 multiplex format and mapping information .............................................................................. 87 internal ring port ............................................................................................................ ......... 93 test access port .............................................................................................................. ........ 94 boundary scan support .................................................................................................... 94 device reset procedure ........................................................................................................ .. 96 memory map .................................................................................................................... ............... 97 memory map descriptions ....................................................................................................... ...... 102 common memory map ........................................................................................................... 10 2 per channel control registers .............................................................................................. 118 per channel status registers ................................................................................................ 12 8 application diagrams .......................................................................................................... .......... 141 package information ........................................................................................................... .......... 142 ordering information .......................................................................................................... ........... 143 related products .............................................................................................................. ............. 143 standards documentation sources ............................................................................................... 144 list of data sheet changes .................................................................................................... ...... 146 documentation update registration form* .............................................................................. 149 * please note that transwitch provides documentation for all of its products. current editions of many documents are available from the products page of the transwitch web site at www.transwitch.com. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking devel- opment of new designs incorporating the product. - 3 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers list of figures figure page 1 t1mx28 txc-04228 block diagram ....................................................................................... 9 2 vt1.5/tu-11 asynchronous and byte-synchronous mappings ............................................ 13 3 t1mx28 txc-04228 lead diagram ...................................................................................... 15 4 tributary input timing ....................................................................................................... .... 33 5 tributary output timing ...................................................................................................... .. 34 6 signaling highway structure ................................................................................................. 3 5 7 serial control port structure and timing .............................................................................. 36 8 telecom bus input timing - 6.48 mhz operation ................................................................. 37 9 telecom bus input timing - 19.44 mhz operation ............................................................... 38 10 telecom bus output timing - 6.48 mhz operation .............................................................. 39 11 telecom bus output timing - 19.44 mhz operation ............................................................ 40 12 datacom mode output timing .............................................................................................. 42 13 datacom mode input timing ................................................................................................. 43 14 intel microprocessor read cycle timing .............................................................................. 44 15 motorola microprocessor read cycle timing ....................................................................... 45 16 intel microprocessor write cycle timing ............................................................................... 46 17 motorola microprocessor write cycle timing ....................................................................... 47 18 boundary scan timing ........................................................................................................ .. 48 19 line interface for dual unipolar mode .................................................................................. 51 20 line interface for nrz mode ................................................................................................. 51 21 byte-synchronous interface to a ds1 framer ...................................................................... 52 22 system interface receive framing format ........................................................................... 54 23 system interface receive signaling format ......................................................................... 54 24 system interface transmit framing format .......................................................................... 56 25 system interface transmit signaling format ........................................................................ 56 26 vt/tu pointer tracking state machine ................................................................................. 65 27 pointer leak rate algorithm ................................................................................................. 70 28 jitter tolerance test setup ................................................................................................. .. 71 29 jitter tolerance measurements ............................................................................................. 72 30 jitter transfer test setup .................................................................................................. .... 73 31 jitter transfer measurements ............................................................................................... 7 3 32 jitter generation test setup ................................................................................................ .74 33 standard pointer test sequences ........................................................................................ 76 34 shadow register operation .................................................................................................. 8 0 35 serial interface operation .................................................................................................. ... 81 36 loopbacks and built-in prbs testing of the t1mx28 .......................................................... 82 37 telecom bus structure; sonet or vc-3 sdh; telecom bus @ 6.48 mhz ......................... 85 38 telecom bus structure; tug-3 sdh; telecom bus @ 19.44 mhz ...................................... 86 39 sts-1 spe mapping ........................................................................................................... .. 87 40 sts-3/au-3 mapping .......................................................................................................... .. 89 41 stm-1/vc-4 mapping .......................................................................................................... .91 42 internal ring port operation ................................................................................................ .93 43 boundary scan schematic .................................................................................................... 9 5 44 typical applications using the t1mx28 ............................................................................... 141 45 t1mx28 txc-04228 456-lead plastic ball grid array package ......................................... 142 - 4 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers features the following features are supported by the t1mx28: the t1mx28 device is a highly-featured twenty-eight-channel ds1 (t1) mapper for use in a wide variety of interface, transmission and switching applications. twenty-eight independent ds1 asynchronous/byte-synchro- nous mappers are provided in a vlsi device using sub-micron cmos technology. powered from a single +3.3 volt supply, the device dissipates less than two watts typically. the t1mx28 is provided in a 456-lead plastic ball grid array package (35 x 35 mm). its ambient operating temperature range extends from -40 c to 85 c with 0 ft/min airflow. the t1mx28 device has been designed to meet the latest industry standards, namely: ansi t1.102- 1993 ansi t1.105- 1991 ansi t1.107- 1995 ansi t1.231 1997 ansi t1.403-1998 at&t pub. 62411 (december 1990) bellcore gr-253-core (issue 2) bellcore tr-nwt-000496 (issue 3) bellcore gr-499-core (issue 1) ieee 1149.1- 1990, -1994 itu -t g.707 3-96 itu -t g.783 features that are independently selectable for each of the mappers line interface options meets ansi and bellcore input jitter requirements rail (for asynchronous mapping only) b8zs or ami ansi compliant los detector ansi compliant ais detector 12-bit bpv counters with excessive zeros option nrz option (for asynchronous and byte-synchronous mapping) clock polarity selection for clock in/out nrz data inversion and clock edge options (separate transmit and receive control) for asynchronous use, negative rail can be used to count externally detected code violations programmable clock edges for transmit and receive data external lead per channel for status (may be programmed to combine with internal ais and los to support external loc detector) clock slave for asynchronous input; clock and multiframe synchronization (3 ms), master or slave, for byte-synchronous input separate signaling highway for byte-synchronous, carries abcd signaling bits and ais/ yellow alarm information in and out of the t1mx28 (see txc-03108, 8-channel t1 framer) - 5 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers external lead-controlled shut down of all ds1 per a or b telecom bus line drive leads for card protection gapped clock option in place of signaling for 1536 khz datacom in byte-synchronous operation crc-6 generation (ds1 input) and error counting (ds1 output) in byte-synchronous mapping mapping and synchronizer features mapping to sonet or sdh columns according to gr-253-core or itu g.709 per channel selectable asynchronous and byte-synchronous mapping to a floating vt1.5 or tu-11 for both mapping and demapping overhead assembly with bip-2 calculation, rei-febe (microprocessor or received bip-2 error), signal label (microprocessor value), rdi (microprocessor value or via received signal label mismatch, vt ais, vt lop, or unequipped) and rfi (microprocessor value or ds1 yellow from signaling highway) pointer calculation (fixed at 78 for asynchronous, calculated for byte-synchronous mode) with generated pointer increment and decrement counters (4 bits each) in byte-synchronous mode, line clock may be an input ( ? modified byte-synchronous mode ? ) or an output ( ? true byte-synchronous mode ? ) multiplexing of signaling bits from the signaling highway with p0/p1 bit generation unequipped and unassigned vt payload generation vt ais generation (microprocessor value, ais from signaling highway, loss of frame on byte- synchronous, or ais/los/external lead from line decoder) threshold modulator to reduce demapping jitter and wander tracking of input multiframe pulses by pointer movements in byte-synchronous mode demapping and desynchronizer features asynchronous or byte-synchronous per channel, programmable to match mapper mode digital pll with 2 hz low pass filter to track up to 250 hz nominal ds1 signal providing a smooth clock output with no need for an external de-jitter buffer separate 5 byte pointer leak buffer with programmable dual slope leak rate (8 ms to 2048 ms per bit in 8 ms steps, automatically doubled to 16 ms to 4096 ms per bit in 16 ms steps within 12 bits of center of pointer leak buffer); meets bellcore mtie with minimal software support power down with all-zeros or all-ones sent to line interface demapping of sonet or sdh columns according to gr-253-core or itu g.709 asynchronous and byte-synchronous demapping of a floating vt1.5/tu-11 pointer tracking and extraction of overhead (v5 and z7/k4), lop, ais, ss and ndf with received pointer increment and decrement counters (4 bits each) overhead processing with bip-2 calculation and error counting (12-bit, with overflow), rei (febe) counting (12-bit, with overflow), rdi (1- and 3-bit)/rfi signal label debouncing and detection, signal label mismatch/unequipped detection demultiplexing of signaling bits to the signaling highway with multiframe generation for byte- synchronous ds1 ais from microprocessor value, vt ais, vt lop, signal label mismatch or unequipped ds1 rai (yellow) to signaling highway from rfi - 6 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers fractional t1 for frame relay, atm aal1 access framer not required for many applications receive and transmit gapped clock (1536 kbit/s) per mapper in byte-synchronous mode crc-6 generation and checking direct connection to multichannel hdlc or atm devices for n x 56 or n x 64 kbit/s service internal dpll to minimize received jitter signaling support for byte-synchronous mapping receive and transmit temporary buffers to align vt1.5/tu-11 payloads to signaling highway signaling bits mapped to and demapped from specific locations per gr-253-core and g.709 a, ab, abcd signaling bit support byte-synchronous operation with transwitch t1fx8 vlsi device: - signaling bit positions in received ds0s optionally replaced with ones by the t1fx8 - vt ais and vt rfi to ds1 ais and ds1 rai (yellow) respectively - ds1 ais and ds1 rai (yellow) to vt ais and vt rfi respectively unicode support (ds0 alarms) for byte-synchronous operation supported by the t1fx8 alarms and errors detection of vt ais, vt rfi, unequipped, signal label mismatch, vt loss of pointer, single-bit rdi, 3-bit rdi, and demap error in the demap direction detection of ds1 ais, loss of signal, map error, and external lead alarm, in the mapping direction counting of code violations (with or without excessive zeros) or crc-6 errors, bip-2, rei (febe), pointer generation and receive pointers with presets and overflow indications microprocessor enable and insert of all alarms detected from line, calculated, or in overhead maintenance loopbacks - ds1 line remote (toward ds1 line), ds1 line local (toward telecom bus), and telecom bus (toward ds1 line for groups of seven channels at once) pbrs generator with 2 15 -1 pattern in transmit framer and analyzer in receive path assignable to any t1 channel - separate control bits with software indication power-down modes force transmit leads to low, high or tristate - 7 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers microprocessor interface nineteen-bit status register for vt ais, vt rfi, unequipped, signal label mismatch, vt loss of pointer, single-bit rdi, 3-bit rdi, ds1 ais, loss of signal, map error, demap error, external lead alarm, and counter overflow bits for code violation/crc-6, bip-2, rei (febe), pointer generation and receive pointers latched event registers and interrupt mask registers to individually control each condition twelve-bit crc-6 (byte-synchronous)/code violation (asynchronous), bip-2, and rei (febe) error counters four-bit increment and decrement pointer generation and receive pointer counters shadow registers for all counters full control of alarm mapping through enable bits microprocessor forcing of alarm conditions per channel reset and resynchronization register access to j2, v5, z6/n2, z7/k4 bytes and o-bits for read and write performance and fault monitoring one second basis, via backplane one second clock shadow registers for all 19 alarms and 7 counters separate registers to indicate alarm changes (performance) and hard conditions (faults) are updated every second to simplify performance report generation features that are only selectable for the twenty-eight mappers as a group telecom bus interface dual add bus and drop bus with individual timing - each bus connected to 14 mappers - paralleled operation for 28 mappers on one bus or multiplexed mapper pair for 14-channel dual bus applications operation at 6.48 mbyte/s or 19.44 mbyte/s compatible with transwitch phast-1, phast-3n, sot-1e and sot-3 devices parity generation and detection with device alarm (odd or even) on data and spe/c1j1v1 sonet mapping via vt1.5 at 6.48 and 19.44 mbyte/s sdh mappings via tu-11 to au-3 at 19.44 mbyte/s uses spe and c1j1v1 to locate individual vts separate sts-1 phases permitted in an sts-3 for asynchronous and modified byte- synchronous operation each transmit and receive time slot is programmable to one of 28 or 84 including internal and external add bus contention monitors with global alarm add bus timing programmable to zero or one clock delay drop or add bus clock edges programmable add bus enable lead plus control leads for optional poh and/or toh drive per vt/tu signal failure input via common lead per telecom bus clock and spe/c1j1v1 presence detectors on system in and system out buses per telecom bus, which generate device alarms on failure - 8 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers external line interface transceiver support four groups of three-wire serial port to read/write control up to seven line interface transceivers ( ? host mode ? ) in each group designed to support integrated microprocessor control of loopbacks, alarms and line build out per channel or broadcast for data out to each group of seven line interface transceivers internal registers to drive and read external devices common microprocessor support microprocessor global reset, masks, polling registers, interrupt polarity and latch edge control motorola split address/data or intel split address/data global alarm indications per group of seven mappers ( ? or ? of per channel alarms of the same type) with a channel pointer register indicating channels with any active alarms global (per group of seven mappers) interrupt mask bits, one per alarm type interrupt on alarm changes: on positive edge, negative edge or both edges - one interrupt line per group of seven mappers device level alarms for telecom bus signals and reference clocks using status and latched event registers with interrupt mask registers device level alarms can be enabled to appear on separate interrupt line per telecom bus for card protection via hardware or software mechanisms error insertion via the microprocessor for parity testing on the telecom bus timed error insertion for rei (febe) and bip-2 global value hardware interrupt polarity selection common hardware reset lead and global (per group of seven mappers) software reset register protection, test and maintenance support ieee 1149.1 boundary scan five lead interface ability to tristate all outputs for in-circuit testing with a single control lead per group of seven mappers loss of clock detectors and parity generator/error detector for add and drop telecom buses internal alarm output programmable to a variety of bus fault and clock fault conditions and a card switch-off feature to assist in implementing protection switching external shadow register clock input (1hz 32 ppm) prbs generator and analyzer per group of seven mappers switchable to any of the seven mapper channels in the group - 9 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers block diagram figure 1. t1mx28 txc-04228 block diagram 8 8 aapar aaadd(1-2) aaclk aac1j1v1 aaspe aad(0-7) adaten abuschk(1-4) adclk adc1j1v1 adspe add(0-7) adfail mastera adpar 8 8 configi 4 telecom bus a 2 1 mapper timing bus a 28 1 14 15 lcsn selip readi/wri wri motoi dtb (0-7) addr (0-8) rdyo/ dtacko intop/ irqop serial port control rfi test tck tdo trs tdi tms 8 9 lsclkp lsdop lsdip t1si pcki highzp aiao tstap tstbp rsti t a p * marks the eight parts of system side line side access port (boundary scan) interface interface readi / prbs gen. & anal. 1 4 microprocessor interface and common control/status i/o 1 4 1 4 biao input timing decoder rx signaling store rx alarm control output timing coder tx signaling store tx alarm control tel bus out ctl tel bus in ctl synchronizer/ mapper clk,mf abcd, fr clk,mf abcd, fr data data 8 inc./dec. & alarms slot timing clk,spe, alarm & control data 8 data slot timing c1j1v1, clk,spe alo, srclk ais,yel & rei (febe) c1j1v1 8 vt termination block ais, rfi to prbs an trib. lpbk facility loopback desynchronizer/ demapper ais los 13 * * * * * * * * telecom bus side tributary side 13 ais, 13 blo from prbs gen note: n=1-28 (channel blocks) 14 alo ring port 4 1 bapar baadd(1-2) baclk bac1j1v1 baspe bad(0-7) bdaten bbuschk(1-4) bdclk bdc1j1v1 bdspe bdd(0-7) bdfail masterb bdpar 8 8 configi 4 telecom bus b 2 1 mapper timing bus b note: p=1-4 (for four groups of seven mappers) 2 2 channel block #1 channel blocks #15-28 channel blocks #1-14 to to lrclkn rsyncn rposn rnegn/ rsigln/ rcvn/ laisn ltclkn tsyncn tposn tnegn/ tsigln/ acso tgcon rgcon bcso the line interface block. interface interface srclk - 10 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers block diagram description a simplified block diagram of the t1mx28 device is shown in figure 1. the major blocks are the twenty-eight channel blocks, the microprocessor interfaces, the serial port control interfaces, the ring ports, the prbs (pseudo-random binary sequence) generators and analyzers, the test access port interfaces, the mapper timing blocks and the telecom bus interfaces for the two 14-channel mapper groups. each of the twenty-eight channel blocks consists of the following component blocks: decoder/coder and input/ output timing (for receive and transmit line interfaces), receive and transmit alarm control, receive and transmit signaling store, synchronizer/mapper and desynchronizer/demapper, vt termination, and telecom bus input and output control blocks. the receive and transmit line interface blocks connect each of the twenty-eight mapper channels to an exter- nal line interface transceiver, which performs the liu and clock recovery functions for the asynchronous mode of operation. the interface to the transceiver can be configured for two interface modes: a dual unipolar (rail) interface or a nrz interface. when the byte-synchronous mode of operation is used, the clock and synchroni- zation signals to and from an external ds1 framer are handled by these blocks; data is then always in the nrz mode.these blocks also provide a tributary (transmit to receive) loopback and a facility or remote (receive line to transmit line) loopback. when the dual unipolar interface mode is selected, input data from the external line interface transceiver is clocked into the t1mx28 on leads rposn and rnegn using the recovered receive clock present on the lrclkn input leads, where n=1-28 identifies one of the twenty-eight mappers (note: rnegn is one of several leads that has multiple functions, with a signal symbol for each). in the transmit direction, unipolar data is clocked out of the t1mx28 on leads tposn and tnegn by the transmit line clock present on the ltclkn out- put leads. global control bits for each group of seven mappers (i.e., channels 1-7, 8-14, 15-21, 22-28) are pro- vided in the memory map which enable the unipolar data to be clocked in and out of the t1mx28 on either edge of the clocks. for the dual unipolar interface mode, the t1mx28 provides either a bipolar with eight zero substitution (b8zs) or an alternate mark inversion (ami), coder and decoder function, and loss of signal detection. the loss of signal detector meets the requirements specified in the ansi t1.231 document listed above in the t1mx28 features section. an unframed ais detector is also provided to assist in network fault iso- lation. a 12-bit performance counter is provided for each mapper, for counting b8zs coding violation errors. an option is provided to also include excessive zeros in the coding violations counter. when the nrz interface mode is selected and the mapper channel is programmed for asynchronous mapping, nrz data is clocked in at the rposn lead by the recovered received clock input on the lrclkn lead. the nrz data is clocked out of the t1mx28 on the tposn leads by the transmit system clock present on the ltclkn leads. global control bits are provided in the memory map for each group of seven mappers which enable the nrz data to be inverted or clocked in and out of the t1mx28 on either edge of the clocks. bipolar violations which are detected in the external line interface transceiver may be clocked into the t1mx28 on the rnegn/rcvn leads and counted in the associated 12-bit coding violation performance counter. the tnegn output may be used in nrz mode as a spare drive bit for applications such as dual bus operation to a single t1 liu. the remote line loopback function for each framer is also implemented in the line interface blocks. when the nrz interface mode is selected and the mapper channel is programmed for byte-synchronous map- ping, nrz data is clocked in at the rposn leads by the clock present on leads lrclkn. the t1mx28 can gen- erate a clock on lrclkn and a 3.0 ms multiframe synchronization signal on leads rsyncn if an external slip buffer is provided in the framer or if the source of the signal is a clock slaved to the t1mx28. if lrclkn and rsyncn are inputs, the t1mx28 translates any clock phase movements with respect to the sonet/sdh clock via vt/tu pointer movements. for applications that do not require a framer but where the ds1 esf crc-6 performance monitoring function is desired (where the t1mx28 is clock master), the t1mx28 calculates and inserts crc-6 into the defined frame bit positions in the vt1.5/tu-11 structure in the mapping direction. after demapping, the crc-6 is checked and any errors found are counted in the 12-bit counter shared for code violation counting. - 11 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers byte-synchronous mapping supports the independent transmission of signaling through defined nibbles in the vt1.5/tu-11 structure, as shown in figure 2. the t1mx28 provides receive and transmit signaling stores to synchronize signaling and framing bits to and from a ds1 framer or switching stage with the mapper and demapper blocks. signaling is received through the rnegn/rsigln leads in byte-synchronous mode, being clocked in with lrclkn. signaling is sent out on the tnegn/tsigln leads in byte-synchronous mode, using ltclkn. transwitch framers like the t1fx8 (txc-03108) can utilize the signaling bits on the signaling high- ways for automatic signaling propagation between sonet/sdh byte-synchronous mapping and ds1 lines. for applications using the full ds1 payload in byte-synchronous mode, the rnegn/rsigln leads can be pro- grammed to supply gapped clock (rgcon), as can the tnegn/tsigln leads (tgcon). the receive and transmit alarm control blocks work in conjunction with the decoder/coder and input/output timing blocks as well as the receive and transmit signaling store blocks to move ds1 alarm signals in and out of the t1mx28. the receive alarm control block detects specific bits from the receive signaling highway, such as ais or rai (yellow), for forwarding to the synchronizer/mapper block as ais and rfi. it also gathers los and ais from the receive line interface. the laisn input lead may be used for forwarding an externally detected loss of signal or loss of clock, or as a general interrupt input. the transmit alarm control block translates rfi and ais from the desynchronizer/demapper block along with microprocessor controls to set specific bits on the transmit signaling highway. transwitch framers like the t1fx8 (txc-03108) can utilize the control bits on the signaling highways for automatic alarm propagation between sonet/sdh and ds1 lines. for card protection schemes, control input leads acso (bcso ), when driven low, cause all of the output leads for the fourteen line interfaces associated with the a or b telecom bus to go low. the synchronizer/mapper block takes the clock and data from the receive line interface in asynchronous mode, threshold modulates it with srclk, buffers it in a fifo, inserts the data bits in the information bit posi- tions of the asynchronous vt1.5/tu-11, and stuffs it using the two stuff opportunity bits with indication in the c1 and c2 bits, as shown in figure 2. the stuffing matches the received ds1 clock to the bit positions avail- able based on the sonet/sdh network clock supplied to the t1mx28 in the add telecom bus clocks, aaclk and baclk, and the aac1j1v1 and bac1j1v1 signals. optional overhead bytes j2, z6/n2, o and part of z7 are taken from microprocessor-written values. the synchronizer/mapper block takes the clock, frame and data from the receive line interface in byte- synchronous mode, buffers it in a fifo and writes it to defined byte positions in the byte-synchronous vt1.5/ tu-11 along with the optional overhead bytes j2, z6/n2 and part of z7, which are taken from microprocessor- written values. for byte-synchronous mode the signaling bits are taken from the receive signaling store and mapped to the correct positions in the vt1.5/tu-11. the 500-microsecond long vt superframe shown in figure 2 is repeated six times, being synchronized to the rsyncn 3.0 millisecond input. the p 1 p 0 bits are generated to indicate which signaling or framing bits are being carried in a specific vt superframe and are related to rsyncn. fifo conditions are monitored and can lead to increment or decrement requests of the vt termination block. synchronization changes in rsyncn are monitored for possible ndf requests. the vt termination block takes the mapped data and optional overhead together with any frame, increment or decrement indications associated with byte-synchronous mode from the synchronizer/mapper block. the v5 and z7 bytes are built from one of several received ds1 alarm sources (the received alarms, ring port error conditions, or microprocessor-written values). parity is then calculated over the payload. v1 and v2 are set to 78, positioning v5 just after v1 for asynchronous mode only. for byte-synchronous mode (true byte-synchro- nous or modified byte-synchronous), the v1 and v2 bytes are generated to track the phase of the incoming ds1 signals relative to aaclk and baclk; two four-bit counters are provided to keep track of pointer incre- ments and pointer decrements generated. if a new position for the rsyncn pulse is generated, this block will generate an ndf along with the new pointer. if the t1mx28 acts as a clock source, the alo or blo lead will be used to provide this clock and it must be frequency locked to the sts-1 or stm-1 clock, or pointer justifications and/or mapping errors will result. if ais is to be generated the entire payload is ones. if unassigned (idle) is to be generated, an all-zeros payload with a valid v5 is generated. if an unequipped is to be generated, an all- zeros payload including v5 is generated. - 12 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers the vt termination block also provides the pointer tracking, v5 and z7 overhead location and vt1.5/tu-11 alarm detection and debouncing functions. the alarms (rdi in four flavors, rfi, unequipped, signal label mis- match, lop, ais, rei, bip-2 errors, etc.) are made available to the common microprocessor block for latching, shadowing, counting and interrupting purposes. alarms are provided on the ring port for rdi and rei to sup- port ring applications. when the t1mx28 is used as a dual bus mapper, a ring port pairs mapper 1 with mapper 15, mapper 2 with mapper 16, etc. for example, transmit alarms for mapper 1 rdi and rei come from mapper 15 rather than from the mapper 1 receive path. it also identifies the payload for the desynchronizer/demapper block as well as any pointer movements. the desynchronizer/demapper block takes the data and alarm information, along with pointer information, and extracts the ds1 signal. this block extracts the optional overhead bytes and sends v5, z6/n2 and z7/k4 to the transmit signaling store. in both modes the data is sent to a pointer leak buffer which is programmable for leak out rate. this is used to minimize jitter and wander on asynchronously mapped signals as well as to smooth out byte-synchronously mapped signals that utilize pointer movements for frequency adjustment. the pointer leak rate may be adjusted to meet mtie requirements with a simple software algorithm which uses the one second latched pointer increment and decrement counters. the desynchronizer uses a dpll operated from the signal on srclk (48.636 mhz) that smooths out the stuffing jitter and compensates for the demapping gapped positions used for all orders of overhead. the desynchronizer outputs a ds1 clock along with the ds1 data to the transmit line interface block ready for transmission or framing without additional de-jittering. in byte-synchronous mode the frame pulse (3.0 ms) is decoded from the p 1 p 0 bits and is used to align the sig- naling highway to the transmit signaling store, and it becomes the signal on tsyncn. a correct p 1 p 0 pattern must be supplied for proper operation even if signaling is not used. alarm information (rfi and ais) is sent to the transmit alarm block for forwarding on the signaling highway. ais is used to cause the dpll to output an in-frequency-range all-ones signal. the telecom bus output and input control blocks buffer the assembled vt1.5/tu-11 bytes for insertion to or extraction from the telecom bus interface. each of the twenty-eight mapper channels can independently be placed on or independently taken from any one of three sts-1s or tug-3s (19.44 mhz telecom bus only), any one of seven vt groups or tug-2s, and any one of four vt1.5 or tu-11s. enable control bits allow a channel to be disconnected in transmit and/or receive from the telecom bus. the two telecom bus interface blocks combine the signals from the twenty-eight mapper channels and syn- chronize them to the add bus half of the telecom bus based on the aaclk, baclk, aac1j1v1, bac1j1v1, aaspe and baspe signals. mappers 1 through 14 are tied to the a bus and mappers 15 through 28 are tied to the b bus. each bus can be configured as a single sts-1 (6.48 mhz), an sts-3 (19.44 mhz) or an stm-1 (19.44 mhz). contention checks are made for the twenty-eight mapper channels; this feature is extended using the abuschk(1-4) and bbuschk(1-4) leads to up to 3 additional t1mx28 devices sharing an add bus. par- ity (leads aapar and bapar) and an add indication (leads aaadd(1-2) and baadd(1-2) ) are included with the byte-wide data (leads aad(0-7) and bad(0-7)). the adaten, bdaten, mastera and masterb leads allow optional drive of overhead and stuff columns, when the data delay option is not used. the drop bus part of the telecom bus provides adclk, bdclk, adc1j1v1(bdc1j1v1), adspe(bdspe) signals along with a failure indication (leads adfail and bdfail) to indicate to the twenty-eight mapper channels that the received data is errored due to higher order path, section or line failures. parity (leads adpar and bdpar) is included with the data (leads add(0-7) and bdd(0-7)). parity covers add and drop data and optionally spe and c1j1v1 signals. all signals are monitored for failure and maskable interrupts may be generated both to the microprocessor interrupt lead and to separate failure leads aiao (biao ). for a 28-channel single bus applica- tion all a bus leads may be connected to all b bus leads. - 13 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers a normal ndf is shown (new data flag = 1001); s1s2 = 11; positive justification = invert the 5 i-bits; negative justification = invert the 5 d-bits; shown msb (bit 1) first. shown msb (bit 1) first. rei-v is also known as febe. rdi-v set to a 1 for unequipped, ais-v and lop-v. 3-bit rdi-v codes: 001 = no defects; 010 = signal label mismatch; 101 = ais-v or lop-v; 110 = unequipped. figure 2. vt1.5/tu-11 asynchronous and byte-synchronous mappings byte-synchronous floating vt mode legend: asynchronous floating vt mode v 1 c q = stuff control v 1 v 5 f = ds1 frame bit v 5 p 1 p 0 s 1 s 2 s 3 s 4 f r i = information r r r r r r i r ds0 channels 1 - 24 j 2 = vt path trace 24 information bytes v 2 o = overhead bits v 2 j 2 p 1 p 0 = signaling phase j 2 p 1 p 0 s 1 s 2 s 3 s 4 f r r = fixed stuff c 1 c 2 o o o o i r ds0 channels 1 - 24 s c = signaling 24 information bytes v 3 st q = stuff opportunity v 3 z 6 v 1 and v 2 = pointer z 6 p 1 p 0 s 1 s 2 s 3 s 4 f r v 3 = inc/dec opportunity c 1 c 2 o o o o i r ds0 channels 1 - 24 24 information bytes v 4 v 4 = unused v 4 z 7 v 5 = vt overhead z 7 p 1 p 0 s 1 s 2 s 3 s 4 f r z 6 = reserved byte c 1 c 2 r r r st 1 st 2 r ds0 channels 1 - 24 z 7 = reserved and 3-bit rdi byte 24 information bytes v1 byte v2 byte new data flag size ididididid 0110s1s2 pointer range = 0 - 103 decimal 1v5 byte8 bip-2 rei-v rfi-v signal label rdi-v 1z7 byte8 rrrr 3-bit rdi-v r - 14 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers the t1mx28 has four prbs generator and analyzer blocks. each generator and analyzer supports the 2 15 -1 pattern. the generator output may be substituted in place of the nrz data stream output from each receive line interface decoder. the analyzer monitors one of the nrz data stream outputs from four groups of seven receive line interface decoders. by setting the telecom bus loopback (a function of the telecom bus inter- face block) and a tributary loopback for one of the twenty-eight channels, the entire channel ? s transmit and receive path can be verified (synchronizer/mapper, vt termination, telecom bus interface, desynchronizer/ demapper, transmit line interface and receive line interface). by moving the loopbacks to framers, lius, vt switches or remote end mappers an entire path can be verified. the serial port control interface blocks provide for communicating with external line interface transceivers that support ? host mode ? operation. this allows the system microprocessor to control the transceiver through the t1mx28. the interface consists of four sets of data output leads (lsdop), clock output leads (lsclkp), and data input leads (lsdip), each shared among a group of seven mappers. each transceiver is selected by the t1mx28, using chip select output signals (lcsn ). in addition, a general purpose input lead (laisn) can be used in nrz mode to generate a maskable interrupt. the test access port block is common to all twenty-eight mapper channels and includes a five-lead test access port (tap) that conforms to the ieee 1149.1 standard. this block provides external boundary scan to read and write the t1mx28 input and output leads from the tap for board and component testing. for non- boundary scan testing the highz p leads are provided to tristate all output leads. the t1mx28 can be configured to operate with either intel or motorola-compatible microprocessors via the microprocessor input/output interface block. separate address, data and control leads are provided. the microprocessor can access four separate 512-byte segments of memory which have individual select and interrupt leads, corresponding to the four groups of seven mappers. interrupt capability is provided with map- per group and individual mapper mask bits as well as activity registers to guide software to the exact cause of an interrupt in the most expeditious manner. a wide variety of alarms is provided on a mapper group level as well as on a per mapper channel level. each alarm or error is reflected in a current status register or counter as well as a latched value register that may be set on the rising, falling or both edges of an alarm. shadow regis- ters for alarms and counters are provided, with the alarm shadow registers doubled to indicate either a change (performance item) or a persistent condition (fault). any latched value may trigger an interrupt, unless it is masked to prevent it causing an interrupt. an option is provided which permits the interrupt polarity to be inverted. an external system clock provided at lead pcki is used to run the internal state machines. - 15 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers lead diagram figure 3. t1mx28 txc-04228 lead diagram note: this is the bottom view. the leads are solder balls. refer to the lead descriptions section below for lead assignment. see figure 45 for package information. a rpnm kjhgfedcb 1 2 3 4 5 6 7 8 9 11 12 13 14 15 t 16 l 17 18 19 20 21 23 22 u ac ab aa y w v 10 ae ad af 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 51 58 51 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 24 25 26 - 16 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers lead descriptions power supply and ground *note: i = input; o = output; p = power per channel tributary i/o (n = 1 to 28); group select (p = 1 to 4) symbol lead no. i/o/p* type name/function vdd l12, l13, l14, l15, m11, m16, n11, n16, p11, p16, r11, r16, t12, t13, t14, t15, p vdd: +3.3 volt supply, 5% gnd a1, a26, l11, l16, m12, m13, m14, m15, n12, n13, n14, n15, p12, p13, p14, p15, r12, r13, r14, r15, t11, t16, af1, af26 p gnd: ground nc ab21 nc : not connected. leave floating. do not make any external connections to this lead. connection may impair perfor- mance or cause damage to the device. symbol lead no. i/o/p type * name/function** lrclkn d4, e4, g5, j3, l5, r5, k4, d23, c21, c19, d17, c16, e14, d12, ab5, ad6, ac8, ac10, ad12, ab14, ab11, ad24, aa23, ab19, u24, t24, r22, u23 i/o cmos line receive clock input: 1.544 mhz 200 hz clock from dsx-1 receiver for asynchronous mapping mode; (tolerance is 50 hz per ansi and bellcore for byte-synchronous oper- ation). global control bit rcaep (bit 6) in register 007h deter- mines the active edge of this clock. input jitter tolerance is 5 ui peak to peak from 10 hz to 500 hz and 0.1 ui peak to peak from 8 khz to 40 khz. see bellcore tr-tsy-000499. for byte-synchronous operation with an external slip buffer for which control bits mode1 and mode0 (bits 1 and 0) in regis- ter x+00h are set to 10, lrclkn is an output derived from leads alo (for p = 1 or 2) and blo (for p = 3 or 4). rsyncn d3, f5, h3, k3, p3, n5, j4, c23, e20, d19, c17, c15, e15, e17, ad4, ac5, ab9, ad9, ad13, ab13, ab7, ab24, ab20, aa22, w23, p24, p22, v23 i/o cmos receive frame sync.: 3.0 millisecond multi-frame sync from framer, or to framer for byte-synchronous mode. sampled on lrclkn falling edge if global control bit rcaep (bit 6) in reg- ister 007h is set to a 0. for byte-synchronous operation with an external slip buffer for which control bits mode1 and mode0 (bits 1 and 0) in regis- ter x+00h are set to 10, rsyncn is an output derived from leads alo (for p = 1 or 2) and blo (for p = 3 or 4). *note: see input, output and input/output parameters section below for type definitions. **note: references to global control bits are for a group of seven channels. these groups are selected by lead selip (p = 1 to 4). individual channel control bits are selected by both lead selip and address offset "x". - 17 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers rposn c3, e5, g3, h4, l3, m4, m3, d24, c22, d20, e18, e16, d14, b11, aa4, ac4, ac7, ab10, ad10, ad14, ab12, ad23, ab22, y22, v24, p25, n23, r24 icmos tributary receive data (positive): nrz/positive rail. ds1 data from framer or dsx-1 receiver. rposn is sampled on lrclkn falling edge if global control bit rcaep (bit 6) in register 007h is set to a 0. in nrz mode, global control bit rxnrzpp (bit 4) in register 007 selects the polarity (a 1 selects a low as a logical one). rnegn/ c4, f4, g4, j5, n3, p5, l4, c24, d21, c20, d18, d15, c13, d13, ac3, ad5, ad7, ac9, ab8, ac14, ac11, ac24, aa24, y23, w24, r25, n22, t23 i/o cmos tributary receive data (negative): negative rail ds1 data from dsx-1 receiver. this lead is sampled on lrclkn falling edge if global control bit rcaep (bit 6) in register 007h is set to a 0. rsigln/ receive signaling highway input: signaling highway from framer. sampled on lrclkn falling edge if global control bit rcaep (bit 6) in register 007h is set to a 0. rcvn tributary receive code violations: code violation counter input. sampled on lrclkn falling edge if global control bit rcaep (bit 6) in register 007h is set to a 0. rgcon receive gapped clock output: when the datacom mode is selected (only available for byte-synchronous operation) via control bit datacom (bit 5) in per channel register x+00h being set to a 1, this lead provides a gapped clock output in which the gap appears at the frame bit times on rposn. laisn c5, e3, f3, j2, k5, n4, m5, e23, d22, e19, c18, d16, c14, c12, ab4, ad3, ac6, ad8, ad11, ac13, ac12, ac23, ab23, y24, w22, u22, p23, t22 icmos line alarm input: line transceiver interrupt, ais or loss of signal/clock from dsx-1 receiver.the active level is deter- mined by global control bit rxnrzpp (bit 4) in register 007, which selects the polarity (a 1 selects a low as a logical one). a per channel control bit explos (bit 6) in register x+00h enables this lead to act as los if set to a 1. control bit los2ais (bit 6) in register x+01h, when set to a 1, causes this signal to propagate vt ais upstream. when explos is set to a 0, status bit xps (bit 7) in register x+10h becomes a separate status indication with latched, mask, performance and fault registers plus global mask and status capability. symbol lead no. i/o/p type * name/function** - 18 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers ltclkn b1, e2, g1, k1, n2, t1, p1, b26, b23, a21, b18, a16, b13, b10, ac1, af2, ae5, af7, af10, af12, ae15, af24, ad26, aa26, y26, t25, k26, m26 ocmos line transmit clock output: 1.544 mhz 200 hz clock to dsx-1 line driver or framer. global control bit tcaep (bit 7) in register 007h determines the active edge of this clock. also see acso (for p = 1 or 2) or bcso (for p = 3 or 4) below. the output frequency tracks the input frequency as defined by the synchronized payload. output jitter caused by de-synchroni- zation and single pointer movements is 0.4 ui or less peak to peak at 10 hz and above (0.075 ui peak to peak or less from 8 khz to 40 khz). tposn b2, d2, f1, j1, m2, y2, r1, c26, b24, a22, b19, a17, b14, a12, ab1, ae2, ae4, af6, af9, ae9, ae14, af23, ae26, ab25, w25, u25, r26, l26 ocmos tributary transmit data (positive): nrz/positive ds1 data to dsx-1 line driver or framer. output on ltclkn rising edge if global control bit tcaep (bit 7) in register 007h is set to a 1. in nrz mode, global control bit txnrzpp (bit 0) in register 007h selects the polarity (a 1 selects a low as a logical one). also see acso (for p = 1 or 2) or bcso (for p = 3 or 4) below. tnegn/ a2, d1, g2, k2, m1, v2, r2, c25, a24, b21, a19, b16, a14, a11, ac2, ae1, af4, ae7, ae10, ae12, af14, ae24, ad25, ab26, w26, u26, n25, l25 ocmos tributary transmit data (negative): negative rail ds1 data to dsx-1 line driver output on ltclkn rising edge if global control bit tcaep (bit 7) in register 007h is set to a 1. when nrz mode is used in asynchronous mode this lead can be used as a spare output (e.g., select b8zs/ami in line i/f transceiver). also see acso (for p = 1 or 2) or bcso (for p = 3 or 4) below. tsigln transmit signaling highway output: signaling highway to framer. output on ltclkn rising edge if global control bit tcaep (bit 7) in register 007h is set to a 1. also see acso (for p = 1 or 2) or bcso (for p = 3 or 4) below. tgcon transmit gapped clock output: when the datacom mode is selected (only available for byte-synchronous operation) via control bit datacom (bit 5) in per channel register x+00h being set o a 1, this lead provides a gapped clock output in which the gap appears at the frame bit times on tposn. symbol lead no. i/o/p type * name/function** - 19 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers tributary common control (p = 1 to 4) tsyncn c2, e1, h2, l2, aa2, u2, p2, b25, a23, b20, a18, b15, a13, a10, ad2, ae3, af5, ae8, ae11, ae13, af15, ae25, ac25, y25, v25, t26, j25, m25 ocmos transmit frame sync: 3.0 millisecond multi-frame sync to framer. output on ltclkn rising edge if global control bit tcaep (bit 7) in register 007h is set to a 1. also see acso (for p = 1 or 2) or bcso (for p = 3 or 4) below. lcsn c1, f2, h1, l1, y1, t2, n1, a25, b22, a20, b17, a15, b12, b9, ad1, af3, ae6, af8, af11, af13, af16, af25, ac26, aa25, v26, r23, k25, n26 ocmos line interface transceiver chip select: an active low signal that enables communications in both directions between the external line interface transceiver for channel n and the t1mx28. this lead is under control of global register 01ah where ensrpp (bit 4) enables transmission to channel n, which is selected by bdcstp (bit 7) to select all channels or the channel selection controls (bits 2-0) which select one of the 7 channels. symbol lead no. i/o/p type name/function alo d26 i cmos bus a local oscillator: 1.544 mhz 32 ppm system clock input used for byte-synchronous mode. 1.544 mhz synchronized to system (aaspe, aaclk and a specific j1 of aac1j1v1) for byte-synchronous operation where lrclk(1-14) and rsync(1-14) are outputs. this signal is also used to generate the serial port clock output lsclkp (for p = 1 or 2). blo ac22 i cmos bus b local oscillator: 1.544 mhz 32 ppm system clock input used for byte-synchronous mode. 1.544 mhz synchronized to system (baspe, baclk and a specific j1 of bac1j1v1) for byte-synchronous operation where lrclk(15-28) and rsync(15-28) are outputs. this signal is also used to generate the serial port clock out- put lsclkp (for p = 3 or 4). srclk t4 i cmos system reference clock: 48.636 mhz 32 ppm (31.5 times 1.544 mhz) system clock input used to operate the synchronizer, desynchronizer, prbs generator/ana- lyzer, and to generate ds1 ais for all twenty-eight chan- nels. symbol lead no. i/o/p type * name/function** - 20 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers lsdop b3, e26, aa1, af22 ocmos line interface transceiver data output signal: com- mon serial control data bus output shared by a group of seven channels. a command byte followed by a data byte, as stored in control registers 017h and 018h respectively, is transmitted to the line interface trans- ceiver selected by lcsn . lsdip d6, e25, y4, ac21 icmos line interface transceiver data input signal: com- mon serial control data bus input shared by a group of seven channels. a data byte coincident with the data byte on lsdop is clocked into the t1mx28 and stored in register 019h from the line interface transceiver selected by lcsn . lsclkp a3, d25, ab2, ae23 ocmos line interface transceiver clock signal: common serial control bus clock output shared by a group of seven channels. a 1.544 mhz clock derived from alo (for p = 1 or 2) or blo (for p = 3 or 4). lsdop is clocked out of the t1mx28 on the falling edge of lsclkp and lsdip is clocked into the t1mx28 on the rising edge of lsclkp. t1si y5 i ttl one second performance clock input: shadow regis- ter latch. this input which is common to all twenty-eight channels, operates the latched counters and pm/fm registers. the following parameter value limits are sug- gested to prevent counters from overflowing when oper- ating in noisy environments or other unfavorable conditions: min. high time 0.50 ms; min. low time 3.0 ms; max. low time 1.5 s. operation at 1.0 hz 32 ppm, 1.0 ms high time, is recommended. this clock is used in conjunction with global control bit enpmfmp (bit 3) in register 006h to clear per channel event registers (not device event registers) after the pm and fm registers have been updated. aiao ab18 o cmos open drain (4 ma) internal alarm output: internal alarm detected, active low output. control bits in registers 01bh and 01ch (for p = 1 or 2), if set to a 1, enable the a side telecom bus clock, payload and synchronous failures, as well as par- ity errors and prbs out of lock, to generate an alarm or interrupt on this lead. biao l22 o cmos open drain (4ma) internal alarm output: internal alarm detected, active low output. control bits in registers 01bh and 01ch (for p = 3 or 4), if set to a 1, enable the b side telecom bus clock, payload and synchronous failures, as well as par- ity errors and prbs out of lock, to generate an alarm or interrupt on this lead. acso r3 i ttl a card switch off: when driven low, ltclk(1-14), tpos(1-14), tneg(1-14)/tsigl(1-14) and tsync(1-14) are driven to a logic low level. symbol lead no. i/o/p type name/function - 21 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers system interface bcso v22 i ttl b card switch off: when driven low, ltclk(15-28), tpos(15-28), tneg(15-28)/tsigl(15-28) and tsync(15-28) are driven to a logic low level. symbol lead no. i/o/p type name/function adclk k24 i ttl drop bus a clock: telecom bus clock for data from system; 6.48 mhz for lead configi tied high or 19.44 mhz for lead configi tied low. control bit tbrcip (bit 4) in registers 01eh (for p = 1 and 2) are set to a 0 selects the rising edge of adclk as the active edge. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. bdclk r4 i ttl drop bus b clock: telecom bus clock for data from system; 6.48 mhz for lead configi tied high or 19.44 mhz for lead configi tied low. control bit tbrcip (bit 4) in registers 01eh (for p = 3 and 4) are set to a 0 selects the rising edge of bdclk as the active edge. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. adc1j1v1 n24 i ttl drop bus a c1j1v1 indicator: telecom bus c1#1, j1#1, or v1#1 valid from system. valid on the rising edge of adclk when control bit tbrcip (bit 4) in regis- ters 01eh (for p = 1 and 2) are set to a 0. used with adspe to identify the start of the payload. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. bdc1j1v1 u3 i ttl drop bus b c1j1v1 indicator: telecom bus c1#1, j1#1, or v1#1 valid from system. valid on the rising edge of bdclk when control bit tbrcip (bit 4) in regis- ters 01eh (for p = 3 and 4) are set to a 0. used with bdspe to identify the start of the payload. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. adspe e24 i ttl drop bus a spe indicator: telecom bus spe valid from system. valid on rising edge of adclk when con- trol bit tbrcip (bit 4) in registers 01eh (for p = 1 and 2) are set to a 0. this signal is high during all vt1.5 or tu- 11 bytes from the system. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. bdspe v1 i ttl drop bus b spe indicator: telecom bus spe valid from system. valid on rising edge of bdclk when con- trol bit tbrcip (bit 4) in registers 01eh (for p = 3 and 4) are set to a 0. this signal is high during all vt1.5 or tu- 11 bytes from the system. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. symbol lead no. i/o/p type name/function - 22 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers add(0-7) m24, h24, e21, l23, h23, j23, k23, m23 ittl drop bus a data: telecom bus data from system; add0 is lsb. valid on rising edge of adclk when con- trol bit tbrcip (bit 4) in registers 01eh (for p = 1 and 2) are set to a 0. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. bdd(0-7) ac19, ad18, ac18, ac20, ad15, ad17, ac17, ac15 ittl drop bus b data: telecom bus data from system; bdd0 is lsb. valid on rising edge of bdclk when con- trol bit tbrcip (bit 4) in registers 01eh (for p = 3 and 4) are set to a 0. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. adpar l24 i ttl drop bus a parity bit: telecom bus parity received over add(0-7), adspe and adc1j1v1. valid on rising edge of adclk when control bit tbrcip (bit 4) in regis- ters 01eh (for p = 1 and 2) are set to a 0; odd/even selectable by control bit tbpep (bit 2) in registers 007h (for p = 1 and 2) when set to a 1, even parity is selected. when control bit tbpisp (bit 3) in registers 007h (for p = 1 and 2) are set to a 0 only add(0-7) is checked for parity. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. bdpar u4 i ttl drop bus b parity bit: telecom bus parity received over bdd(0-7), bdspe and bdc1j1v1. valid on rising edge of bdclk when control bit tbrcip (bit 4) in regis- ters 01eh (for p = 3 and 4) are set to a 0; odd/even selectable by control bit tbpep (bit 2) in registers 007h (for p = 3 and 4) when set to a 1, even parity is selected. when control bit tbpisp (bit 3) in registers 007h (for p = 3 and 4) are set to a 0 only bdd(0-7) is checked for parity. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. adfail j24 i ttl drop bus a signal fail: signal fail indication valid on the rising edge of adclk when control bit tbrcip (bit 4) in registers 01eh (for p = 1 and 2) are set to a 0. if adfail is high the specific vt slot contains invalid data (add(0-7)); the per vt alarms are invalid and are masked; ds1 ais is generated. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. bdfail w3 i ttl drop bus b signal fail: signal fail indication valid on the rising edge of bdclk when control bit tbrcip (bit 4) in registers 01eh (for p = 3 and 4) are set to a 0. if bdfail is high the specific vt slot contains invalid data (bdd(0-7)); the per vt alarms are invalid and are masked; ds1 ais is generated. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. symbol lead no. i/o/p type name/function - 23 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers aaclk h26 i ttl add bus a clock: telecom bus clock for data to sys- tem; 19.44 mhz for lead configi tied high or 6.48 mhz for lead configi tied low. when control bit tbtcip (register 01eh, bit 5) (for p = 1 and 2) is set to a 0, the aaspe and aac1j1v1 signals are clocked in on the ris- ing edge of aaclk. the falling edge of aaclk is used to clock the aad(0-7), aapar and aaadd signals out to the add bus so that these signals can be sampled on the next rising edge. when tbtcip = 1 the opposite clock edges are used. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. baclk ad19 i ttl add bus b clock: telecom bus clock for data to sys- tem; 19.44 mhz for lead configi tied high or 6.48 mhz for lead configi tied low. when control bit tbtcip (register 01eh, bit 5) (for p = 3 and 4) is set to a 0, the baspe and bac1j1v1 signals are clocked in on the ris- ing edge of baclk. the falling edge of baclk is used to clock the bad(0-7), bapar and baadd signals out to the add bus so that these signals can be sampled on the next rising edge. when tbtcip = 1 the opposite clock edges are used. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. aac1j1v1 g25 i ttl add bus a c1j1v1 indicator: te l e c o m b u s c 1 # 1 , j1#1, v1#1 valid for data to system. this signal is sam- pled on the rising edge of aaclk when control bit tbtcip (register 01eh, bit 5) (for p = 1 and 2) is set to a 0. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. bac1j1v1 w1 i ttl add bus b c1j1v1 indicator: te l e c o m b u s c 1 # 1 , j1#1, v1#1 valid for data to system. this signal is sam- pled on the rising edge of baclk when control bit tbtcip (register 01eh, bit 5) (for p = 3 and 4) is set to a 0. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. aaspe f25 i ttl add bus a spe indicator: telecom bus spe valid for data to system. this signal is sampled on the rising edge of aaclk when control bit tbtcip (register 01eh, bit 5) (for p = 1 and 2) is set to a 0. this signal is high during all vt1.5 or tu-11 bytes to the system. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. baspe w2 i ttl add bus b spe indicator: telecom bus spe valid for data to system. this signal is sampled on the rising edge of baclk when control bit tbtcip (register 01eh, bit 5) (for p = 1 and 2) is set to a 0. this signal is high during all vt1.5 or tu-11 bytes to the system. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. symbol lead no. i/o/p type name/function - 24 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers aad(0-7) b4, a5, b5, a6, b6, a7, b7, a8 o(t) ttl 4ma add bus a data: telecom bus data to system; aad0 is lsb. the t1mx28 will output the data on the falling edge of aaclk when control bit tbtcip (register 01eh, bit 5) (p = 1 and 2) is set to a 0. control bit tbddp (bit 3) in registers 01eh (for p = 1 and 2) selects zero aaclk clock period delay if set to a 0 and a single aaclk clock period delay if set to a 1. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. these signals are in the tristate condition when the t1mx28 is not driving the add bus. bad(0-7) af21, ae21, af20, ae20, af19, ae19, af18, ae18 o(t) ttl 4ma add bus b data: telecom bus data to system; bad0 is lsb. the t1mx28 will output the data on the falling edge of baclk when control bit tbtcip (register 01eh, bit 5) (p = 3 and 4) is set to a 0. control bit tbddp (bit 3) in registers 01eh (for p = 3 and 4) selects zero baclk clock period delay if set to a 0 and a single baclk clock period delay if set to a 1. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. these signals are in the tristate condition when the t1mx28 is not driving the add bus. aapar a9 o(t) ttl 4ma add bus a parity bit: telecom bus parity generated for any aad(0-7), aaspe and aac1j1v1 placed on the telecom bus. the t1mx28 will output parity on the fall- ing edge of aaclk when control bit tbtcip (register 01eh, bit 5) (for p = 1 an 2) is set to a 0. control bit tbpep (register 007h, bit 2) (for p = 1 an 2) selects odd/ even parity. when tbpep is set to a 0, odd parity is selected. when control bit tbpisp (bit 3) in registers 007h (for p = 1 and 2) are set to a 0 only aad(0-7) is included in the parity calculation. control bit tbddp (bit 3) in registers 01eh (for p = 1 and 2) selects zero aaclk clock period delay if set to a 0 and a single aaclk clock period delay if set to a 1. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. this signal is in the tristate condition when the t1mx28 is not driving the add bus. symbol lead no. i/o/p type name/function - 25 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers bapar ae17 o(t) ttl 4ma add bus b parity bit: telecom bus parity generated for any bad(0-7), baspe and bac1j1v1 placed on the telecom bus. the t1mx28 will output parity on the fall- ing edge of baclk when control bit tbtcip (register 01eh, bit 5) (p = 3 and 4) is set to a 0. control bit tbpep (register 007h, bit 2) (p = 3 and 4) selects odd/even par- ity. when tbpep is set to a 0, odd parity is selected. when control bit tbpisp (bit 3) in registers 007h (for p = 3 and 4) is set to a 0 only bad(0-7) is included in the parity calculation. control bit tbddp (bit 3) in registers 01eh (for p = 3 and 4) selects zero baclk clock period delay if set to a 0 and a single baclk clock period delay if set to a 1. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. this signal is in the tristate condition when the t1mx28 is not driv- ing the add bus. aaadd(1-2) b8, a4 o ttl 4ma add bus a add data present indicator: telecom bus device outputs valid. this signal goes low on the falling edge of aaclk when control bit tbtcip, register 01eh, bit 5 (for p = 1 and 2) is set to a 0. this signal is active when the t1mx28 writes to the telecom bus, allowing for external drivers to be used. control bit tbddp (bit 3) in registers 01eh (for p = 1 and 2) selects zero aaclk clock period delay if set to a 0 and a single aaclk clock period delay if set to a 1. control bits must be set to the same value for both p = 1 and p = 2 for proper operation. this signal is high when the t1mx28 is not driving the add bus a. baadd(1-2) ae22, af17 o ttl 4ma add bus b add data present indicator: telecom bus device outputs valid. this signal goes low on the falling edge of baclk when control bit tbtcip register 01eh, bit 5 (for p = 3 and 4) is set to a 0. this signal is active when the t1mx28 writes to the telecom bus, allowing for external drivers to be used. control bit tbddp (bit 3) in registers 01eh (for p = 3 and 4) selects zero baclk clock period delay if set to a 0 and a single baclk clock period delay if set to a 1. control bits must be set to the same value for both p = 3 and p = 4 for proper operation. this signal is high when the t1mx28 is not driving the add bus b. abuschk (1-4) c7, c6, g26, f26 i ttl add bus a check: used to determine if another t1mx28 on the same telecom bus is driving in the same slot. each abuschk(1-4) input is connected to the aaadd(1-2) of the same or another t1mx28. if a colli- sion is detected, status bit tbxesp (bit 0) in register 00bh is set to a 1. latched value, mask pm, and fm register bits are also supplied. see operations section for dual or single bus connections. symbol lead no. i/o/p type name/function - 26 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers microprocessor interface (p = 1 to 4) bbuschk (1-4) y3, aa3, ad22, ad20 ittl add bus b check: used to determine if another t1mx28 on the same telecom bus is driving in the same slot. each bbuschk(1-4) input is connected to the baadd(1-2) of the same or another t1mx28. if a colli- sion is detected, status bit tbxesp (bit 0) in register 00bh is set to a 1. latched value, mask pm, and fm register bits are also supplied. see operations section for dual or single bus connections. mastera d5 i ttlp add bus a master: when tied to ground, poh and stuff columns are driven to zero on aad(0-7) with correct parity. see the telecom bus operations subsection. masterb ab3 i ttlp add bus b master: when tied to ground, poh and stuff columns are driven to zero on bad(0-7) with correct parity. see the telecom bus operations subsection. adaten f24 i ttl add bus a data enable: when high, aad(0-7), aapar and aaadd(1-2) are enabled. it is normally tied to aaspe to float the telecom bus during toh. bdaten ad21 i ttl add bus b data enable: when high, bad(0-7), bapar and baadd(1-2) are enabled. it is normally tied to baspe to float the telecom bus during toh. configi j26 i ttl add/drop bus configuration input: configuration of the telecom bus. for configi high, both telecom buses are 28 slot/6.48 mhz. for configi low, both telecom buses are 84 slot/19.44 mhz. symbol lead no. i/o/p type name/function rsti ab17 i ttlp hardware reset: device reset. this active low signal will reset all twenty-eight ds1 mappers. it should be held low for a minimum of 4 clock periods of pcki. motoi e8 i ttl motorola mode: motorola - intel microprocessor mode select. high selects motorola. low selects intel. dtb(0-7) d11, d10, e10, d9, d8, c9, e9, d7 i/o ttl 8ma data: microprocessor bidirectional, tristate data bus; dtb0 is lsb. addr(0-8) g22, j22, g23, h22, h5, k22, c11, c10, e11 i ttl address bus: microprocessor address bus; addr0 is lsb. symbol lead no. i/o/p type name/function - 27 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers boundary scan and test port (p = 1 to 4) selip e13, m22, p4, ab15 i ttlp select: microprocessor interface select. a low selects the interface for each group of seven mappers and allows the transfer of information between the t1mx28 and the microprocessor. when p = 1, channels 1-7 are addressed. when p = 2, channels 8-14 are addressed. when p = 3 channels 15-21 are addressed. when p = 4 channels 22-28 are addressed. readi / readi/wri u5 i ttl read: read or read/write. intel: low to read t1mx28. motorola: high to read/low to write. wri e7 i ttl write: intel mode only; low to write to t1mx28. rdyo/ c8 o(t) ttl 8ma ready: intel mode: a high acknowledges that data transfer can take place this cycle. a low indicates wait states. dtacko data transfer acknowledge: motorola mode: a low during read indicates data bus is valid. a low during write indicates data is accepted. intop/ e12, h25, u1, ae16 o ttl 4ma interrupt: intel mode: if control bit ipolp (bit 4) in register 006h is set to a 0, a high indicates an interrupt request to the microprocessor from the group of seven channels indicated by the lead (p = 1 channels 1-7, p = 2 channels 8-14, etc.). irqop interrupt request: motorola mode: if control bit ipolp (bit 4) in register 006h is set to a 0, a low indicates an interrupt request to the microprocessor from the group of seven channels indicated by the lead (p = 1 channels 1-7, p = 2 channels 8-14, etc.). pcki e6 i ttl processor clock: processor clock input. required for device operation; 8 to 20 mhz. t1mx28 will continue to pass data on loss of pcki, but microprocessor access will be blocked. symbol lead no. i/o/p type name/function tck t5 i ttl test clock: ieee 1149.1 boundary scan clock input. this clock is used to shift data into tdi on the rising edge and out of tdo on the falling edge. tdi t3 i ttlp test data input: boundary scan data input. serial test instructions and data are clocked into this lead on the rising edge of tck. tdo p26 o(t) ttl 4ma test data output: boundary scan data output. serial data and test instructions are clocked out of this lead on the falling edge of tck. symbol lead no. i/o/p type name/function - 28 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers tms w5 i ttlp test mode select: boundary scan test mode select input; sampled by tck rising edge to put t1mx28 into test mode. trs e22 i ttlp test reset: boundary scan reset input. this lead will asynchronously reset the test access port (tap) con- troller if held low for a minimum duration of 300 ns. this lead is to be held low, asserted low or pulsed low to reset the tap controller on t1mx28 power-up. highzp v5, g24, w4, ad16 icmos high impedance select: grounding these leads causes all outputs except tdo to go to a high imped- ance for the group of seven mappers chosen, but alters no internal registers. tstap v3, f23, ab6, ab16 icmos test a: device test leads. must be connected to ground. tstbp v4, f22, aa5, ac16 icmos test b: device test leads. must be connected to ground. symbol lead no. i/o/p type name/function - 29 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the "caution" label on the drypack bag in which devices are supplied. 3. v in may not exceed the actual operating supply voltage (v dd ) by more than 0.5 volts. 4. test method for esd per mil-std-883d, method 3015.7. thermal characteristics power requirements parameter symbol min max unit conditions supply voltage v dd -0.3 3.9 v note 1 dc input voltage v in -0.5 v dd + 0.5 v notes 1, 3 storage temperature range t s -40 150 o cnote 1 ambient operating temperature t a -40 85 o c 0 ft/min linear airflow moisture exposure level me 5 tbd level per eia/jedec jesd22-a112-a relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd absolute value 1500 v note 4 parameter min typ max unit test conditions thermal resistance: junction to ambient 14 o c/w 0 ft/min linear airflow. parameter min typ max unit test conditions v dd 3.15 3.30 3.45 v i dd 400 1 500 2 ma 1.) asynchronous mapping to a 6.48 mhz telecom bus. 2.) byte-synchronous mapping to a 19.44 mhz telecom bus. power dissipation, p dd 1320 1 1725 2 mw - 30 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers input, output and input/output parameters input parameters for cmos input parameters for ttl input parameters for ttlp note: input has a 9k (nominal) internal pull-up resistor. parameter min typ max unit test conditions v ih 0.7 x v dd v 3.15 < v dd < 3.45 v il 0.3 x v dd v 3.15 < v dd < 3.45 input leakage current 10 av in = 3.45 input capacitance (leads alo and blo) 5.0 pf input capacitance (lead srclk) 10 pf input capacitance (all other leads) 2.5 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current 10 a input capacitance (leads abuschk(1-4) and bbuschk(1-4) ) 2.5 pf input capacitance (leads acso , bcso and all system interface input leads not listed above or below) 5.0 pf input capacitance (lead configi and all other leads) 10 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current 0.5 1.0 ma v in = 3.45; input = 0 volts input capacitance (leads rsti , tms and trs ) 10 pf input capacitance (all other leads) 2.5 pf - 31 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers output parameters for cmos or ttl 4 ma output parameters for cmos open drain (4 ma) note: open drain requires use of 4.7k ohm external pull-up resistor. if this resistor is not provided the output behaves as tri state. output parameters for ttl 8 ma parameter min typ max unit test conditions v oh 2.4 v v dd = 3.15; i oh = -4.0 v ol 0.4 v v dd = 3.15; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 11 ns c load = 50 pf t fa l l 7.0 ns c load = 50 pf leakage tristate 10 a 0 to 3.45 v input parameter min typ max unit test conditions v ol 0.5 v v dd = 3.15; i ol = 4.0 i ol 4.0 ma t fall 7.0 ns c load = 50 pf high z leakage current 10 av in = 3.45 parameter min typ max unit test conditions v oh 2.4 v v dd = 3.15; i oh = -8.0 v ol 0.4 v v dd = 3.15; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 6.0 ns c load = 50 pf t fa l l 4.0 ns c load = 50 pf - 32 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers input/output parameters for cmos input/output parameters for ttl 8 ma parameter min typ max unit test conditions v ih 0.7 x v dd v dd + 0.5 v 3.15 < v dd < 3.45 v il 0.3 x v dd v3.15 < v dd < 3.45 input leakage current 10 av dd = 3.45 input capacitance 2.5 pf v oh 2.4 v v dd = 3.15; i oh = -4.0 v ol 0.4 v v dd = 3.15; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 6.0 ns c load = 50 pf t fa l l 4.0 ns c load = 50 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current 10 av in = 3.45 input capacitance (leads dtb(0-7)) 10 pf v oh 2.4 v v dd = 3.15; i oh = -8.0 v ol 0.4 v v dd = 3.15; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 6.0 ns c load = 50 pf t fa l l 4.0 ns c load = 50 pf - 33 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers timing characteristics detailed timing diagrams for the t1mx28 are illustrated in figures 4 through 18, with values of the timing inter- vals tabulated below each diagram. all output times are measured with a maximum 25 pf load capacitance, unless otherwise indicated. timing parameters are measured at voltage levels of (v oh + v ol )/2 for output sig- nals or (v ih + v il )/2 for input signals. figure 4. tributary input timing notes: 1. for true byte-synchronous mode (control bits mode0 and mode1 = 01) lrclkn and rsyncn are outputs. for the other modes lrclkn and rsyncn are inputs. 2. lrclkn active edge may be inverted via control bit rcaep (bit 6) in register 007h; as shown rcaep = 0. rposn, rnegn, rsigln, rsyncn and rcvn are clocked in on the falling edge of lrclkn. for true byte-synchronous mode of operation, lrclkn and rsyncn are outputs. rsyncn is output delayed from the rising edge of lrclkn when control bit rcaep = 0. parameter symbol min typ max unit lrclkn clock period t cyc 560 648 ns lrclkn high time t pwh 240 ns lrclkn low time t pwl 240 ns rposn/rnegn/rsigln/rcvn setup time to lrclkn t su(1) 50 ns rposn/rnegn/rsigln/rcvn hold time after lrclkn t h(1) 50 ns rsyncn pulse width as input t pw 500 750 ns rsyncn pulse width as output t pw 560 648 ns rsyncn setup as input before lrclkn t su(2) 50 ns rsyncn hold as an input after lrclkn t h(2) 50 ns rsyncn delay as output after lrclkn t d 50 ns t cyc t pwh t pwl t su(1) t h(1) t d t pw lrclkn rposn rsyncn rcvn rsigln rnegn t su(2) t h(2) note: n=1-28 (see notes 1, 2) (inputs) (see notes 1, 2) - 34 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 5. tributary output timing * ltclkn may be inverted via control bit tcaep (bit 7) in register 007h; as shown tcaep = 1. parameter symbol min typ max unit ltclkn clock period t cyc 637 648 656 ns ltclkn duty cycle, t pwh /t cyc -- 45 55 % tposn/tnegn/tsigln output delay after ltclkn t od -5.0 50 ns tsyncn delay after ltclkn t d -5.0 50 ns tsyncn pulse width t pw 637 648 656 ns t cyc t od t d t pw lt c l k n * tposn tsyncn tsigln tnegn note: n=1-28 t pwh - 35 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 6. signaling highway structure * tsyncn or rsyncn should be valid on the active edge of ltclkn or lrclkn, respectively. parameter symbol min typ max unit tsyncn/rsyncn clock period (n=1-28) t cyc 3.000 ms tsyncn/rsyncn pulse width (n=1-28) t pw one clock period of lt c l k n o r lrclkn* ns --- ds0 1 lsb s1/c1 msb f1/m1 ds0 lsb ds0 ds0 1 msb ds0 1 a1 lrclkn lt c l k n rsyncn tsyncn 24 ds0 24 ds0 1 ds0 1 ds0 1 24 ds0 1 ds0 1 ds0 1 ds0 1 ais ais a2 a3 a4 yel ais a5 a6 a8 yel a7 rposn/ tposn/ rsigln* tsigln* 4630 4631 0 1 2 3 4 5 192 193 194 195 196 197 198 multi-frame bit number multi-frame 24 * 1 * 2 note 1: * shown for 16-state signaling. see operation section. f1/m1 a1 ais ais a2 a3 a4 yel s1/c1 ais a5 a6 a8 yel a7 note 2: "---" in tposn, tnegn, rposn, rnegn, rsigln, and tsigln are unused bits (see operation section). note 3: ais is present in ds0 bit positions 16 through 192 (ds0 3 - ds0 24); bits 6 through 15 are unused. t cyc t pw --- --- --- --- --- -- rnegn tnegn note: n=1-28 - 36 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 7. serial control port structure and timing parameter symbol min typ max unit lsclkp clock period t cyc 560 648 ns lsclkp high time t pwh 280 ns lsclkp low time t pwl 280 ns lcsn delay time to lsclkp t d(1) 100 324 350 ns lcsn inactive pulse width t pw 300 ns lsdip setup time to lsclkp t su 100 ns lsdip hold time after lsclkp t h(1) 100 ns lsclkp to lcsn inactive t h(2) 100 ns lsdop delay after lsclkp t d(2) 100 ns lsclkp rise and fall times (10% - 90%) t r , t f 50 ns lcsn lsclkp lsdip lsdop t pwh t cyc t pwl t su t h(1) t d(2) t h(2) t d(1) addrd0d1d2d3d4d5 d6 d7 t pw r/w addr addr addr addr addr addr data input/output address/command byte d0 d1 d2 d3 d4 d5 d6 d7 note: n=1-28, p=1-4 - 37 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 8. telecom bus input timing - 6.48 mhz operation * for gapped clock applications, skipping a rising (and next falling) edge of adclk(bdclk) will extend the current low time to twice the listed value. all data is clocked in on the rising clock edge unless control bit tbrcip (bit 4) in register 01eh is set to a 1, in which case all data is clocked in on the falling clock edge. parameter symbol min typ max unit adclk(bdclk) clock period t cyc 150 154.32 ns adclk(bdclk) high time t pwh 38 116 ns adclk(bdclk) low time t pwl 38 116* ns add(0-7)(bdd(0-7))/adpar(bdpar) setup time to adclk(bdclk) t su(1) 7.0 ns add(0-7)(bdd(0-7))/adpar(bdpar) hold time after adclk(bdclk) t h(1) 6.0 ns adspe(bdspe) setup time to adclk(bdclk) t su(2) 7.0 ns adspe(bdspe) hold time after adclk(bdclk) t h(2) 6.0 ns adc1j1v1(bdc1j1v1) setup time to adclk(bdclk) t su(3) 7.0 ns adc1j1v1(bdc1j1v1) hold time after adclk(bdclk) t h(3) 6.0 ns adc1j1v1(bdc1j1v1) pulse width for c1 t pw 120 ns c1 j1, v1#1 j1 v5 v4#1 c1 a1 t cyc t pwh t pwl t h(1) t su(1) t h(2) adclk add(0-7) adpar adspe adc1j1v1 t pw t su(3) t h(3) t su(2) bdclk bdc1j1v1 bdspe bdd(0-7) ddpar (input) (input) (input) (input) a2 v1#1 - 38 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 9. telecom bus input timing - 19.44 mhz operation * for gapped clock applications, skipping a rising (and next falling) edge of adclk(bdclk) will extend the current low time to twice the listed value. all data is clocked in on the rising clock edge unless control bit tbrcip (bit 4) in register 01eh is set to a 1, in which case all data is clocked in on the falling clock edge. parameter symbol min typ max unit adclk(bdclk) clock period t cyc 50 51.44 ns adclk(bdclk) high time t pwh 23 29 ns adclk(bdclk) low time t pwl 23 29* ns add(0-7)(bdd(0-7))/adpar(bdpar) setup time to adclk(bdclk) t su(1) 7.0 ns add(0-7)(bdd(0-7))/adpar(bdpar) hold time after adclk(bdclk) t h(1) 6.0 ns adspe(bdspe) setup time to adclk(bdclk) t su(2) 7.0 ns adspe(bdspe) hold time after adclk(bdclk) t h(2) 6.0 ns adc1j1v1(bdc1j1v1) setup time to adclk(bdclk) t su(3) 7.0 ns adc1j1v1(bdc1j1v1) hold time after adclk(bdclk) t h(3) 6.0 ns adc1j1v1(bdc1j1v1) pulse width for an individual pulse (e.g., isolated j1) t pw 40 ns adc1j1v1(bdc1j1v1) j1#1 to v1#1 delay (sts-3 mode) t d 3 cycles of adclk(bdclk) ns adc1j1v1(bdc1j1v1) j1#1 to v1#1 delay (stm-1 mode) t d 6 cycles of adclk(bdclk) ns c1#1 j1#1 v1#1 j1#1 v1#1 v5 v4#1 c1#1 a1 t cyc t pwh t pwl t h(1) t su(1) t h(2) adclk add(0-7) adpar adspe adc1j1v1 t pw t su(3) t h(3) t su(2) bdclk bdc1j1v1 bdspe bdd(0-7) bdpar (input) (input) (input) (input) t d - 39 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 10. telecom bus output timing - 6.48 mhz operation * for gapped clock applications, skipping a rising (and next falling) edge of aaclk(baclk) will extend the current low time to twice the listed value. if control bit tbtcip (bit 5) in register 01eh is set to a 0, all data is clocked in on the rising aaclk(baclk) c lock edge and out on the falling aaclk(baclk) clock edge, as is shown in the timing diagram. if control bit tbtcip = 1, all data is clocked i n on the falling clock edge and out on the rising clock edge of aaclk(baclk). if control bit tbddp = 1, aad(0-7)(bad(0-7)), aapar(bapar) and aaadd(1-2) (baadd(1-2) ) are delayed one clock period from what is shown in the timing diagram with reference to aaspe(baspe) and aac1j1v1(bac1j1v1); input to adaten(bdaten) must also be delayed one clock period of aaclk(baclk). parameter symbol min typ max unit aaclk(baclk) clock period t cyc 150 154.32 ns aaclk(baclk) high time t pwh 38 116 ns aaclk(baclk) low time t pwl 38 116* ns aad(0-7)(bad(0-7))/aapar(bapar) delay time after aaclk(baclk) t d(1) 3.0 20 ns aad(0-7)(bad(0-7))/aapar(bapar) float time after aaclk(baclk) t f 3.0 20 ns aaspe(baspe) setup time to aaclk(baclk) t su(1) 7.0 ns aaspe(baspe) hold time after aaclk(baclk) t h(1) 3.0 ns aac1j1v1(bac1j1v1) setup time to aaclk(baclk) t su(2) 7.0 ns aac1j1v1(bac1j1v1) hold time after aaclk(baclk) t h(2) 3.0 ns aad(0-7)(bad(0-7))/aapar(bapar) delay time after adaten(bdaten) t d(2) 16 ns aad(0-7)(bad(0-7))/aapar(bapar) delay time after adaten(bdaten) t d(3) 14 ns aaadd(1-2) (baadd(1-2) ) delay time after adaten(bdaten) t d(4) 13 ns aaadd(1-2) (baadd(1-2) ) delay time after adaten(bdaten) t d(5) 13 ns aaadd(1-2) (baadd(1-2) ) delay time after aaclk(baclk) t d(6) 0.0 18 ns aac1j1v1(bac1j1v1) pulse width for c1 t pw 120 ns aad(0-7)(bad(0-7))/aapar(bapar) rise/fall times (10% - 90%) t r , t f 12 ns c1 j1, v1#1 j1 v1#1 v5 data c1 a1 t cyc t pwh t pwl t h(2) t su(1) aaclk aad(0-7) aapar aaspe aac1j1v1 t pw t d(4) t su(2) adaten t d(1) t d(6) t d(5) t d(2) t d(3) aaadd(1-2) t f t h(1) baclk bac1j1v1 baspe bad(0-7) bapar baadd(1-2) bdaten (input) (output) (input) (input) (output) (input) a2 - 40 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 11. telecom bus output timing - 19.44 mhz operation parameter symbol min typ max unit aaclk(baclk) clock period t cyc 50 51.44 ns aaclk(baclk) high time t pwh 23 29 ns aaclk(baclk) low time t pwl 23 29* ns aad(0-7)(bad(0-7))/aapar(bapar) delay time after aaclk(baclk) t d(1) 3.0 20 ns aad(0-7)(bad(0-7))/aapar(bapar) float time after aaclk(baclk) t f 3.0 20 ns aaspe(baspe) setup time to aaclk(baclk) t su(1) 7.0 ns aaspe(baspe) hold time after aaclk(baclk) t h(1) 3.0 ns aac1j1v1(bac1j1v1) setup time to aaclk(baclk) t su(2) 7.0 ns aac1j1v1(bac1j1v1) hold time after aaclk(baclk) t h(2) 3.0 ns aad(0-7)(bad(0-7))/aapar(bapar) delay time after adaten(bdaten) t d(2) 16 ns aad(0-7)(bad(0-7))/aapar(bapar) delay time after adaten(bdaten) t d(3) 14 ns aaadd(1-2) (baadd(1-2) ) delay time after adaten(bdaten) t d(4) 13 ns aaadd(1-2) (baadd(1-2) ) delay time after adaten(bdaten) t d(5) 13 ns aaadd(1-2) (baadd(1-2) ) delay time after aaclk(baclk) t d(6) 0.0 18 ns aac1j1v1(bac1j1v1) pulse width for an individual pulse (e.g., isolated j1) t pw 40 ns c1#1 j1#1 v1#1 v5 data c1#1 a1 t cyc t pwh t pwl t h(2) t su(1) aaclk aad(0-7) aapar aaspe aac1j1v1 t pw t d(4) t su(2) adaten t d(1) t d(6) t d(5) t d(2) t d(3) aaadd(1-2) t f t h(1) baclk bac1j1v1 baspe bad(0-7) bapar baadd(1-2) bdaten (input) (output) (input) (input) (output) (input) j1#1 v1#1 t d(7) - 41 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers * for gapped clock applications, skipping a rising (and next falling) edge of aaclk(baclk) will extend the current low time to twice the listed value. if control bit tbtcip (bit 5) in register 01eh is set to a 0, all data is clocked in on the rising aaclk(baclk) c lock edge and out on the falling aaclk(baclk) clock edge, as is shown in the timing diagram. if control bit tbtcip = 1, all data is clocked i n on the falling clock edge and out on the rising clock edge of aaclk(baclk). if control bit tbddp = 1, aad(0-7)(bad(0-7)), aapar(bapar) and aaadd(1-2) (baadd(1-2) ) are delayed one clock period from what is shown in the timing diagram with reference to aaspe(baspe) and aac1j1v1(bac1j1v1); input to adaten(bdaten) must also be delayed one clock period of aaclk(baclk). aad(0-7)(bad(0-7))/aapar(bapar) rise/fall times (10% - 90%) t r , t f 12 ns aac1j1v1(bac1j1v1) j1#1 to v1#1 delay (sts-3 mode) t d(7) 3 cycles of aaclk(baclk) ns aac1j1v1(bac1j1v1) j1#1 to v1#1 delay (stm-1 mode) t d(7) 6 cycles of aaclk(baclk) ns parameter symbol min typ max unit - 42 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 12. datacom mode output timing notes: 1. ltclkn can be inverted with the control bit tcaep (bit 7) in register 007h. 2. ltclkn shown with tcaep set to a 0. 3. 25 pf load. parameter symbol min typ max unit ltclkn period t cyc 637 648 656 ns delay - ltclkn 1,2 to tgcon t d(1) 0.0 10 ns delay - ltclkn to tposn or tsyncn t d(2) -5.0 50 ns fall time (90% - 10%) 3 ? ltclkn, tgcon, tposn or tsyncn t f 6.0 ns ltclkn or tgcon high time t pwh 40% 50% 55% t cyc ltclkn or tgcon low time t pwl 40% 50% 55% t cyc rise time (10% - 90%) 3 - ltclkn, tgcon, tposn or tsyncn t r 6.0 ns t pwl t pwh t cyc t r t f t d(1) ds0 24, lsb f bit time lt c l k n tposn tsyncn ds0 1, msb tgcon (tneg) t d(2) note: n=1-28 - 43 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 13. datacom mode input timing notes: 1. lrclkn active edge may be inverted via control bit rcaep (bit 6) in register 007h; as shown rcaep = 1. rposn, rnegn, rsigln, rsyncn and rcvn are clocked in on the falling edge of lrclkn. for true byte-synchronous mode of operation, lrclkn and rsyncn are outputs. rsyncn is output delayed from the rising edge of lrclkn when control bit rcaep = 0. 2. lrclkn shown with rcaep set to a 1. 3. 25 pf load. 4. when rsyncn is an output, it is delayed from the falling edge of lrclkn when rcaep is set to a 1. parameter symbol min typ max unit lrclkn period t cyc 560 648 ns delay - lrclkn 1,2 to rgcon t d(1) 0.0 10 ns delay - lrclkn 1,2 to rsyncn if output t d(2) 50 ns fall time (90% - 10%) 3 ? rgcon, and lrclkn or rsyncn if outputs t f 6.0 ns hold - rposn or rsyncn if input after lrclkn 1,2 t h 50 ns lrclkn or rgcon high time t pwh 240 ns lrclkn or rgcon low time t pwl 240 ns rise time (10% - 90%) 3 - rgcon, and lrclkn or rsyncn if outputs t r 6.0 ns setup - rposn or rsyncn if input to lrclkn 1,2 t su 50 ns t pwl t pwh t cyc t r t f t d(1) lrclkn rsyncn rgcon t d(2) note: n=1-28 rposn rsyncn (output) (input) t su t h lsb f bit time msb ds0 24 ds0 1 (see note 1) (see note 4) - 44 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 14. intel microprocessor read cycle timing *note: pcki (not shown) is processor clock input, 8 to 20 mhz, which is required for device operation. parameter symbol min typ max unit addr(0-8) setup time to selip t su(1) 0.0 ns dtb(0-7) valid delay after rdyo t d(1) -1/2 cycle pcki* -10 ns dtb(0-7) float time after readi t f 1.0 3.0 5.0 ns selip setup time to readi t su(2) 0.0 ns readi pulse width t pw(1) 50 ns selip hold time after readi t h 0.0 ns rdyo delay after readi t d(2) 0.0 12 ns rdyo pulse width t pw(2) 2 cycles of pcki* 6 cycles of pcki* ns addr(0-8) dtb(0-7) selip readi rdyo t h t f t d(1) t pw(2) t d(2) t su(2) t su(1) t pw(1) - 45 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 15. motorola microprocessor read cycle timing *note: pcki (not shown) is processor clock input, 8 to 20 mhz, which is required for device operation. parameter symbol min typ max unit dtb(0-7) float time after selip t f(1) 1.0 10 ns addr(0-8) valid setup time to selip t su(1) 0.0 ns readi/wri setup time to selip t su(2) 0.0 ns selip pulse width t pw(1) 50 ns dtacko pulse width t pw(2) 2 cycles of pcki* 6 cycles of pcki* ns dtb(0-7) output delay after dtacko t d(1) -1/2 cycle pcki* -10 ns dtacko float time after selip t f(2) 1.0 10 ns dtacko delay after selip t d(2) 0.0 12 ns addr(0-8) dtb(0-7) selip readi/wri dtacko t f(2) t f(1) t d(1) t pw(2) t su(2) t su(1) t pw(1) t d(2) - 46 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 16. intel microprocessor write cycle timing *note: pcki (not shown) is processor clock input, 8 to 20 mhz, which is required for device operation. wait states only occur if a write cycle immediately follows a previous read or write cycle (e.g. ? read modify write ? or word-wide write). parameter symbol min typ max unit dtb(0-7) valid setup time to wri t su(1) 20 ns dtb(0-7) hold time after wri t h(1) 5.0 ns addr(0-8) setup time to selip t su(2) 0.0 ns selip setup time to wri t su(3) 0.0 ns wri pulse width t pw(1) 50 ns rdyo delay after wri t d 0.0 12 ns rdyo pulse width t pw(2) 0.0 6 cycles of pcki* ns addr(0-8) dtb(0-7) selip wri rdyo t h(1) t su(2) t pw(2) t d t su(3) t pw(1) t su(1) - 47 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 17. motorola microprocessor write cycle timing *note: pcki (not shown) is processor clock input, 8 to 20 mhz, which is required for device operation. wait states only occur if a write cycle immediately follows a previous read or write cycle (e.g. ? read modify write ? or word-wide write). parameter symbol min typ max unit dtb(0-7) valid setup time to selip t su(1) 20 ns dtb(0-7) valid hold time after selip t h(1) 5.0 ns addr(0-8) valid setup time to selip t su(2) 0.0 ns addr(0-8) valid hold time after selip t h(2) 3.0 ns readi/wri setup time to selip t su(3) 0.0 ns selip pulse width t pw(1) 50 ns dtacko pulse width t pw(2) 0.0 6 cycles of pcki* ns dtacko float time after selip t f 1.0 10 ns dtacko delay after selip t d 0.0 12 ns addr(0-8) dtb(0-7) selip readi/wri t f t pw(2) t su(2) t su(3) dtacko t su(1) t h(1) t pw(1) t d t h(2) - 48 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 18. boundary scan timing parameter symbol min max unit tck clock high time t pwh 50 ns tck clock low time t pwl 50 ns tms setup time to tck t su(1) 3.0 - ns tms hold time after tck t h(1) 2.0 - ns tdi setup time to tck t su(2) 3.0 - ns tdi hold time after tck t h(2) 2.0 - ns tdo delay from tck t d -7.0ns tms tdi tdo t d tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t pwl - 49 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers operation general mapper application overview the t1mx28 can be used in a wide variety of applications that require either an asynchronous mapping of a ds1 signal into and out of a sonet or sdh payload in which the input clock and data are replicated at the output, or a byte-synchronous mapping of a ds1 signal into or out of a sonet or sdh payload in which not only is the input clock and data replicated at the output, but ds0 visibility and signaling information is replicated at the output. when used in an asynchronous application the ds1 side of the mapper connects to the line through ds1 line interface units (lius) that recover the 1.544 mhz clock from the received data, provide clock and data to the t1mx28, input clock and data from the t1mx28 and format a line signal for transmission. four ports are provided to control up to 28 lius from the t1mx28. when used in byte-synchronous applications, ds1 framers (like the transwitch t1fx8) may be inserted between the lius and the t1mx28 to delineate the ds0s, extract and insert signaling, process ds0 and ds1 alarms, etc. the byte-synchronous applications may also be used for direct interface to sources of ds0s (e.g., time slot interchangers, pcm codecs) or to data sources like fractional t1 with hdlc protocol on n x ds0 channels (like the transwitch mchdlc). the t1mx28 provides complete clock recovery of ds1 signals through a two stage digital filter, eliminating the need for special external de-jitter buffers while still meeting the stringent bellcore mtie requirements. the t1mx28 provides complete sonet or sdh low order path termination and origination functions (vt1.5/ tu-11) with alarm mapping to and from the ds1 line. on the system side, all that is required is a high order section, line and path termination/origination function. the telecom bus provided in the t1mx28 allows for multiple devices to be connected seamlessly to a transwitch phast-1, sot-3 or phast-3n device, all of which supply these high order functions. microprocessor access is provided for optional overhead bytes. for redundant and ring applications an internal ring i/o support port is provided as well as special alarm output and ds1 isolation input. a microprocessor port is provided to configure the t1mx28 as well as to provide interrupts for device-wide/telecom bus alarms as well as vt1.5/tu-11 or ds1 alarms. one second shadow registers are provided to assist in the preparation of performance monitoring information. an ieee 1149.1 boundary scan function and an internal prbs generator/analyzer are provided for board test support. line interface selection each of the twenty-eight t1mx28 channels can be individually programmed for asynchronous mode, byte-syn- chronous mode as clock master, or a modified byte-synchronous mode where the t1mx28 channel is a clock slave in which pointer movements are generated as needed to map the incoming ds1 signal to the sonet/ sdh payload. the table below details the options present at the line interface. mode of operation line code rnegn tnegn mode1 mode0 lcode encod datacom x+00 bit 1 x+00 bit 0 x+00 bit 3 x+00 bit 2 x+00 bit 5 asynchronous ami data data 0 x 0 1 x asynchronous b8zs data data 0 x 1 1 x asynchronous nrz rcvn low 0 x 0 0 x asynchronous nrz rcvn high 0 x 1 0 x byte-synchronous lrclk/rsyncn out nrz rsigln input tsigln output 10xx 0 - 50 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers note: x=don ? t care asynchronous operation with the line interface each of the twenty-eight mapper channels in the t1mx28 can be programmed to provide either a dual unipolar interface or a nrz interface. the dual unipolar interface is selected when a 1 is written into control bit encod (bit 2) in the control register located at address x+00h in the memory map. the x is (n x 040h), where n is the number of the mapper selected (1-28), as explained in the memory map section. the b8zs line or ami coder/ decoder (codec) feature can be selected for the dual unipolar interface. the b8zs codec is selected by writing a 1 to control bit lcode (bit 3) in the register x+00h. a 0 will select an ami codec. the b8zs stands for bipolar with eight zero substitution, which is described in ansi document ansi t1.102-1993 and other bellcore documents. the clock polarity of the input and output line clocks is selectable by writing the sense required to global control bits tcaep and rcaep (bits 7 and 6) in register 007h. when a mapper is configured for the dual unipolar mode, the line signal is monitored for loss of signal (los). los is detected if no transitions are present for 175 75 pulse positions. recovery occurs when a ones density of 12.5% or more is detected in 175 75 pulse positions. a status bit loss (bit 5) in register x+10h indicates this condition. a mask, losm, a latched value, lose, a pm value, lospm and a fm value, losfm are available (bit 5) at register locations x+08h, x+14h, x+18h and x+1ch respectively. coding violations are counted in a 12-bit performance counter located at reg- ister locations x+22h and x+23h with shadow value in registers x+2ah and x+2bh. a counter overflow bit cvos (bit 0) in register x+10h is provided. a mask, cvom, a latched value, cvoe, a pm value, cvopm and a fm value, cvofm are available (bit 0) at register locations x+08h, x+14h, x+18h and x+1ch respectively. excessive zeros (8 or more for b8zs or 16 or more for ami) are included if control bit enzc (bit 4) in register x+00h is set to a 1. an ais indication is provided which checks to see if more than 99.9% ones occur in a 3 to 75 millisecond period. no ais indication is provided if less than 99.9% ones occur in a 3 to 75 millisecond period. status bit daiss (bit 3) in register x+10h indicates the ais condition. a mask, daism, a latched value, daise, a pm value, daispm and a fm value, daisfm are available (bit 3) at register locations x+08h, x+14h, x+18h and x+1ch respectively. the los condition can also be used to generate an ais (ds1 pay- load all-ones will be mapped in place of the received signal) if control bit los2ais (bit 6) in register x+01h is set to a 1. the coder block provides an ami/b8zs encoder. this block provides ais generation either from the micropro- cessor interface by control bit sdaisl (bit 3) in register x+03h when set to a 1 or optionally from various sys- tem conditions (vt ais/lop, signal label mismatch or unequipped) all of which are individually enabled by control bits vais2ais (bit 3 at x+01h), slm2ais (bit 2 at x+02h) and une2ais (bit 0 at x+02h) being set to a 1. a high level signal failure input on leads adfail and bdfail will cause ds1 ais for all twenty-eight map- pers. a 'transmit all-zeros' capability is provided to conserve power in an external line transceiver when ais is not required by setting control bit sdaisl (bit 3) in register x+03h to a 0 when control bit tbrval (bit 7) in reg- ister x+04h is also set to a 0 (drop slot not assigned). the connections between a t1mx28 mapper and exter- nal line interface transceivers are shown in figure 19 below for dual unipolar mode. byte-synchronous (datacom) lrclk/rsyncn out nrz rgcon output tgcon output 10xx 1 modified byte-synchronous lrclk/rsyncn in nrz rsigln input tsigln output 11xx 0 modified byte-synchronous (datacom) lrclk/rsyncn in nrz rgcon output tgcon output 11xx 1 mode of operation line code rnegn tnegn mode1 mode0 lcode encod datacom x+00 bit 1 x+00 bit 0 x+00 bit 3 x+00 bit 2 x+00 bit 5 - 51 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 19. line interface for dual unipolar mode the nrz interface is selected when a 0 is written into control bit encod (bit 2) in register x+00h. the clock polarity of the line input and output clocks is selectable by writing to global control bits tcaep and rcaep (bits 7 and 6) in register 007h. options are provided for inverting the polarity of the transmit and receive data leads. a 1 written to control bit txnrzpp (bit 0) in global register 007h inverts the polarity of the transmit data signal, tposn, while a 1 written to control bit rxnrzpp (bit 4) in the same register inverts the polarity of the receive data signal rposn. in nrz mode, the rnegn lead may be used to input an external indication of coding vio- lations (rcvn). external coding violations are counted in the same 12-bit performance counter as described above. coding violations are counted when the input is high for rising edges of the line clock lrclkn. the same ais detector as described above for bipolar is available in nrz mode. los can be detected only exter- nally and input on lead laisn. by setting control bit explos (bit 6) in register x+00h to a 1, loss status plus latched event, mask, pm and fm functions are provided as described above. in the transmit direction, when the nrz mode is selected, the tnegn lead becomes a spare drive lead. when control bit encod (bit 2) in register x+00h is a 0, the output state of tnegn is defined by the value written to bit lcode (bit 3) in register x+00h (lcode set to a 0 is a low on tnegn and lcode set to a 1 is a high on tnegn). a typical interface between a mapper in the t1mx28 and an external line transceiver is shown in figure 20 below for the nrz mode. tnegn, for example, may be used to select the encoding mode for the liu. figure 20. line interface for nrz mode line interface t1mx28 receive rposn rnegn lrclkn tposn tnegn lt c l k n lcsn laisn lsclkp lsdop lsdip cs los sclk sdi sdo rxtip rxring txtip txring transmit note: n is the channel number (1 - 28) and p is the group (of seven mappers) number (1 - 4) other tr a n s c e i v e r s for channel n transceiver line interface tr a n s c e i v e r for channel n t1mx28 receive rposn rcvn lrclkn tposn tnegn lt c l k n lcsn laisn lsclkp lsdop lsdip cs los sclk sdi sdo rxtip rxring txtip txring transmit note: n is the channel number (1 - 28) and p is the group (of seven mappers) number (1 - 4) other transceivers - 52 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers byte-synchronous operation with the line interface for byte-synchronous operation the line interface operates in the nrz mode with rsigln and tsigln carrying the signaling information from/to an external framer using the negative polarity input and output leads. figure 21 is the basic byte-synchronous setup. typical applications are shown in figure 44. in byte- synchronous applications where signaling is not used, a datacom option is provided for connections to hdlc controllers or other devices that operate over the ds1 payload only. tgco and rgco are gapped clock outputs for clocking out or in data on tposn and rposn. the clock is gapped during the frame bit time every 125 ms. this option is available by setting control bit datacom (bit 5) in register x+00h to a 1. for byte-synchronous applications that require ds1-based performance monitoring (control bits mode1, mode0 =10 in register x+00h bits 1 and 0 only), crc-6 is generated optionally for each superframe of data presented on rposn and inserted in the cn frame bit locations of the following superframe to be mapped. when control bit crc6 (bit 4) in register x+01h is set to a 1 crc-6 is both inserted and checked. after demapping crc-6 is checked. crc-6 errors share the 12-bit line code violation counter shadow register and overflow indications to support performance monitoring. crc-6 errors are counted in the 12-bit performance counter located at register locations x+22h and x+23h with shadow value in registers x+2ah and x+2bh. each esf superframe in which a calculated crc-6 value does not match the received crc-6 value incre- ments the counter by one. a counter overflow bit cvos (bit 0) in register x+10h is provided. a mask, cvom, a latched value, cvoe, a pm value, cvopm and a fm value, cvofm are available (bit 0) at register locations x+08h, x+14h, x+18h and x+1ch respectively. figure 21. byte-synchronous interface to a ds1 framer receive data and signaling highway operation the receive highway carries information from the framer to the t1mx28. the highway is sub-divided into two time division multiplexed buses, one for the data (rposn), and one for signaling, frame bit and alarms (rsigln). these two buses are synchronous with the signals lrclkn and rsyncn, a 1.544 mhz clock and a 3 millisecond synchronization signal driven from the framer or the t1mx28 depending on the mode of byte-syn- chronous operation. if the t1mx28 operates in the modified byte-synchronous mode, receive clock and syn- chronization are inputs to the t1mx28; if the t1mx28 operates in true byte-synchronous mode, receive clock and synchronization are outputs of the t1mx28. the data highway is a single-bit serial bus organized into 193- bit groups called frames. each frame consists of a spare bit position followed by twenty-four 8-bit data samples representing the 24 ds0s. 24 frames form a multiframe, the beginning of which is identified by a synchroniza- tion pulse, rsyncn. the rsyncn high pulse occurs one bit time before the first frame of the multiframe and every 24 frames after that. the signaling highway, rsigln, is also divided into 193-bit frames. each frame con- sists of a frame bit followed by 192 bits of signaling and alarm information for the 24 data channels on the data highway. the frame bit pattern tracks the signaling bit pattern received from the system. the alarm bits in the signaling highway follow the signaling bits. in each frame of 193 bits, four signaling bits are transmitted followed by a rai (yellow) alarm bit position. the bit positions coincident with ds0 3 through ds0 24 are all used for the t1mx28 receive rprxtosn rsigln/rgcon lrclkn tsigln/tgcon tposn lt c l k n rxtip rxring txtip txring transmit note: n is the channel number (1 - 28) ds1 framer and liu tsyncn rsyncn or other ds0 device - 53 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers ais alarm bit. signaling bits a1 through a4 occur in frame number one, followed by a5 through a8 in frame number two, and so on, ending with d21 through d24 in frame number 24, corresponding to the esf mode with 16-state signaling. for two-state or four-state signaling the b, c and d bits or the c and d bits are replaced by a bits or a and b bits respectively, as shown in the following table. the receive framing format and signaling format are shown in figures 22 and 23. the signaling information is stored in the rx signaling store block for mapping. the alarm information (ds1 ais and ds1 rai-yellow) is stored in the rx alarm control block and can be enabled to generate vt ais or rfi automatically. control bit sh2vais (bit 7) in register x+01h, when set to a 1, causes the ais alarm bits on the signaling highway to activate vt ais generation for the affected channel. when control bit yel2rfi (bit 1) in register x+01h is set to a 1, the rai-yellow alarm bit on the signaling highway causes the t1mx28 mapper channel to send a vt rfi in the v5 byte. the status of these two signaling highway alarm bits is available as shdais and shyel (bits 7 and 6) in register x+20h as status only. when control bit ais2vais (bit 0) in register x+01h is set to a 1, the t1mx28 will cause vt ais to be generated if the ds1 ais condition as defined above for the asynchronous mode of operation is detected. when control bit datacom (bit 5) in register x+00h is set to a 1, rsigln input becomes rgcon output, which is a gapped lrclkn clock with a gap of one lrclkn cycle wide occurring at the frame bit time of rposn every 125 microseconds. signaling bit positions on rsigln and tsigln frame sf/esf 16-st. rsigl; s 1 -s 4 tsigl; s 1 -s 4 4-state; s 1 -s 4 2-state; s 1 -s 4 1 f1/m1 a01, a02, a03, a04 a01, a02, a03, a04 a01, a02, a03, a04 a01, a02, a03, a04 2 s1/c1 a05, a06, a07, a08 a05, a06, a07, a08 a05, a06, a07, a08 a05, a06, a07, a08 3 f2/m2 a09, a10, a11, a12 a09, a10, a11, a12 a09, a10, a11, a12 a09, a10, a11, a12 4 s2/f1 a13, a14, a15, a16 a13, a14, a15, a16 a13, a14, a15, a16 a13, a14, a15, a16 5 f3/m3 a17, a18, a19, a20 a17, a18, a19, a20 a17, a18, a19, a20 a17, a18, a19, a20 6 s3/c2 a21, a22, a23, a24 a21, a22, a23, a24 a21, a22, a23, a24 a21, a22, a23, a24 7 f4/m4 b01, b02, b03, b04 b01, b02, b03, b04 b01, b02, b03, b04 a01, a02, a03, a04 8 s4/f2 b05, b06, b07, b08 b05, b06, b07, b08 b05, b06, b07, b08 a05, a06, a07, a08 9 f5/m5 b09, b10, b11, b12 b09, b10, b11, b12 b09, b10, b11, b12 a09, a10, a11, a12 10 s5/c3 b13, b14, b15, b16 b13, b14, b15, b16 b13, b14, b15, b16 a13, a14, a15, a16 11 f6/m6 b17, b18, b19, b20 b17, b18, b19, b20 b17, b18, b19, b20 a17, a18, a19, a20 12 s6/f3 b21, b22, b23, b24 b21, b22, b23, b24 b21, b22, b23, b24 a21, a22, a23, a24 13 f1/m7 c01, c02, c03, c04 c01, c02, c03, c04 a01, a02, a03, a04 a01, a02, a03, a04 14 s1/c4 c05, c06, c07, c08 c05, c06, c07, c08 a05, a06, a07, a08 a05, a06, a07, a08 15 f2/m8 c09, c10, c11, c12 c09, c10, c11, c12 a09, a10, a11, a12 a09, a10, a11, a12 16 s2/f4 c13, c14, c15, c16 c13, c14, c15, c16 a13, a14, a15, a16 a13, a14, a15, a16 17 f3/m9 c17, c18, c19, c20 c17, c18, c19, c20 a17, a18, a19, a20 a17, a18, a19, a20 18 s3/c5 c21, c22, c23, c24 c21, c22, c23, c24 a21, a22, a23, a24 a21, a22, a23, a24 19 f4/m10 d01, d02, d03, d04 d01, d02, d03, d04 b01, b02, b03, b04 a01, a02, a03, a04 20 s4/f5 d05, d06, d07, d08 d05, d06, d07, d08 b05, b06, b07, b08 a05, a06, a07, a08 21 f5/m11 d09, d10, d11, d12 d09, d10, d11, d12 b09, b10, b11, b12 a09, a10, a11, a12 22 s5/c6 d13, d14, d15, d16 d13, d14, d15, d16 b13, b14, b15, b16 a13, a14, a15, a16 23 f6/m12 d17, d18, d19, d20 d17, d18, d19, d20 b17, b18, b19, b20 a17, a18, a19, a20 24 s6/f6 d21, d22, d23, d24 d21, d22, d23, d24 b21, b22, b23, b24 a21, a22, a23, a24 - 54 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 22. system interface receive framing format figure 23. system interface receive signaling format rsyncn lrclkn f = frame bit; frame 1 frame 2 frame 3 frame 24 one frame (193 bits) channel 1 channel 2 channel 3 channel 24 rposn 8 bits per channel f s 1 s 2 s 3 s 4 y-- - -------- aaaaaaaa aaaaaaaa aaaaaaaa a = ais; y = rai-yellow alarm; s1, s2, s3, s4 = signaling bits; - = not assigned 3 ms rsigln - rsyncn lrclkn frame 1 frame 2 frame 23 frame 24 first 5 bits rsigln 3 ms of frame first 5 bits of frame first 5 bits of frame first 5 bits of frame first 5 bits of frame f a 0 1 a 0 4 a 0 2 a 0 3 f a 0 5 a 0 8 a 0 6 a 0 7 f c 0 5 c 0 8 c 0 6 c 0 7 f d 1 7 d 2 0 d 1 8 d 1 9 f d 2 1 d 2 4 d 2 2 d 2 3 rposn - 55 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers transmit data and signaling highway operation the transmit highway carries information from the t1mx28 to the framer. the highway is sub-divided into two time division multiplexed buses, one for the data (tposn) and one for signaling, frame bits and alarms (tsigln). these two buses are synchronous with the signal ltclkn, a 1.544 mhz clock that is driven from the t1mx28. the data highway is a single bit-serial bus that is organized into 193-bit groups called frames. each frame consists of a frame bit followed by twenty-four 8-bit data samples. each of the 8-bit data samples repre- sents a single ds0 on the receive highway. the 193-bit frames are grouped into a 24-frame multiframe. in order to help locate the beginning of a frame and extract signaling information, the t1mx28 sources a synchro- nization signal, tsyncn. in byte-synchronous mode only; tsyncn is present if a standard compliant p 1 p 0 pattern is present in the vt1.5 or tu-11 as shown in figure 2. the tsyncn high pulse occurs one bit time before the first frame in the multiframe and every 24 frames after that. the signaling highway, tsigln, is also divided into 193-bit frames and is organized in an identical fashion to rsigln (see the table above for signaling bit assignments). the alarm bits in the signaling highway follow the signaling bits. in each frame of 193 bits, four signaling bits are transmitted followed by a rai (yellow) alarm bit position. the bit positions coincident with ds0 3 through ds0 24 are all used for the ais alarm bit. signaling bits a1 through a4 occur in frame number one followed by a5 through a8 in frame number two ending with d21 through d24 in frame number 24, corre- sponding to the esf mode with 16-state signaling. for two-state or four-state signaling the b, c and d bits or the c and d bits are replaced by a bits or a and b bits respectively, as shown in the table above. ais or yellow alarm sourced by the t1mx28 are output in the same positions as on rsigln. these alarm bits may be used to force ds1 yellow or ds1 ais automatically in the t1fx8. control bit vais2ais (bit 3) in register x+01h, when set to a 1, causes the detection of vt-lop or vt ais to set the ais bits on tsigln unless control bit datacom (bit 5) in register x+00h is set to a 1. similarly, if control bits slm2ais (bit 2) and une2ais (bit 0) in register x+02h are set to a 1, and if either a signal label mismatch or unequipped condition exists, the ais bits on the signaling highway are set to a 1 unless control bit datacom is set to a 1. setting control bit sdaisl (bit 3) in register x+03h to a 1 will also set the ais bits in tsigln unless control bit datacom is set to a 1. control bit sdaisl set to a 1 or control bits vais2ais, slm2ais or une2ais set to a 1 and the condition vt lop/ais, signal label mismatch or unequipped occurs will cause an all-ones signal to be generated on tposn without regard for control bits datacom or mode1. likewise, the yellow alarm bit on the signaling highway may be set if control bit rfi2yel (bit 2) in register x+01h and an rfi alarm is detected, or if control bit syell (bit 2) in register x+03h is set to a 1 when control bit mode1 (bit 1) in register x+00h is set to a 1 indicating byte-synchronous operation and datacom (bit 5) in the same register is set to a 0 indicating tsigln is not used for gapped clock output. the frame bits received from the vt1.5/tu-11 are available on tsigln as well; they track the signaling bits and may be used for fdl extraction. when control bit datacom (bit 5) in register x+00h is set to a 1, tsigln output becomes tgcon output, which is a gapped ltclkn clock with a gap one ltclkn cycle wide occurring at the frame bit time of tposn every 125 microseconds. system interface transmit framing format and signaling format are shown as figures 24 and 25. - 56 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 24. system interface transmit framing format figure 25. system interface transmit signaling format the tx signaling store and the tx alarm control blocks buffer the signaling and alarm information to be sent on the signaling highway. the signaling bits are output as shown in the table above as well as in figure 25. to support certain protection schemes, leads acso and bcso when tied low will cause the transmit line inter- face leads (ltclkn, tnegn/tsigln/tgcon, tposn, and tsyncn) to be driven to a logic low. f = frame bit; frame 1 frame 2 frame 3 frame 24 one frame (193 bits) channel 1 channel 2 channel 3 channel 24 8 bits per channel f s 1 s 2 s 3 s 4 y-- - -------- aaaaaaaa aaaaaaaa aaaaaaaa a = ais; y = yellow alarm; s1, s2, s3, s4 = signaling bits; - = not assigned 3 ms tsyncn ltclkn tposn tsigln f tsyncn ltclkn frame 1 frame 2 frame 23 frame 24 first 5 bits tsigln 3 ms of frame first 5 bits of frame first 5 bits of frame first 5 bits of frame first 5 bits of frame f a 0 1 a 0 4 a 0 2 a 0 3 f a 0 5 a 0 8 a 0 6 a 0 7 f c 0 5 c 0 8 c 0 6 c 0 7 f d 1 7 d 2 0 d 1 8 d 1 9 f d 2 1 d 2 4 d 2 2 d 2 3 tposn - 57 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers the synchronizer, mapper and overhead generator the synchronizer/mapper block operates in three different modes, programmable on a per channel basis as described above in the line interface section. the synchronizer/mapper is the heart of the mapping side of the device. it synchronizes the 1.544 mb/s data stream to the sonet/sdh clock domain, it maps the data stream to the virtual tributary (vt1.5/tu-11) and it inserts the low order path overhead for performance moni- toring and administrative purposes. figure 2 shows the result of the synchronization, mapping and overhead insertion functions to form a vt1.5/tu-11 for asynchronous or byte-synchronous mode. the synchronization function adjusts approximately 772 ds1 bits so that they fit into a vt1.5/tu-11 which is 500 microseconds long. the ds1 signal, whether framed to sf or esf formats or framed to another format, generates 193 bits every 125 microseconds. as shown in figure 2, three opportunities are provided for 193 bits (i plus 24 bytes) and one opportunity for 192 (no st bits used for information), 193 (one st bit used for infor- mation) or 194 bits (both st bits used for information) in the vt1.5/tu-11 for the asynchronous mode. two stuffing control bits (c 1 and c 2 ) repeated twice are provided in every vt1.5/tu-11 to indicate if a stuffing bit opportunity is to be used for information or stuff; for c 1 c 1 c 1 = 000 indicates that s t1 is used for an information bit and c 1 c 1 c 1 = 111 indicates that s t1 is used for a stuff bit. c 2 is treated likewise. this mechanism allows majority voting to be used at the desynchronizer, providing a robust solution at high bit error rates. the t1mx28 has an input buffer that is written by the ds1 line clock and read by the sonet/sdh clock. the stuffing control in the t1mx28 uses the depth of this input buffer to set the value of c 1 and c 2 . buffer overflow/underflow is a fault condition of the input caused by the input frequency being outside the stuffing range for asynchronous mapping (approximately 230 hz). this condition will be passed to the microprocessor interface as an alarm (map error). status bit mps (bit 4) in register x+10h indicates the map error status; mask mpm, latched event mpe, performance value mppm and hard fault value mpfm are all bit 4 of registers x+08h, x+14h, x+18h and x+1ch respectively. the stuffing mechanism in the t1mx28 employs threshold modulation such that a desynchronizer will meet gr-253-core category i jitter requirements. this is done by using srclk to vary the input ds1 clock ? s phase for every sequential vt1.5/tu-11 such that the stuffing pattern varies at a fre- quency high enough to be filtered easily by the desynchronizer. this prevents a ds1 clock that is a few hz dif- ferent from a sonet/sdh derived 1.544 mhz reference clock from generating jitter spikes when desynchronized. this feature can be turned off for testing purposes by setting global control bit tmdisp (bit 2) in register 03dh to a 1. byte-synchronous mapping permits full ds0 and signaling visibility as is shown in figure 2. the 24 bytes every 125 microseconds are now 24 ds0s; the stuffing mechanism is replaced by a p 1 /p 0 pattern that is used to identify different sf and esf frame bits as well as which signaling bits are being sent and which go to what ds0s. byte-synchronous mapping performs synchronization in two different ways. when lrclkn and rsyncn are outputs they are derived from signal alo(blo), which must be sourced from the sonet/sdh payload timing (aaclk(baclk), aaspe(baspe) and aac1j1v1(bac1j1v1)). as such, exactly 24 ds0s, one frame bit and four signaling bits are mapped every 125 microseconds. rsyncn output defines the start of the first of six vt superframes (the p 1 /p 0 pattern goes from 11 to 00) that form a 3.0 ms multiframe. if the source of the ds1 has a different clock than at leads alo(blo), an external slip buffer must be provided; the transwitch t1fx8 (txc-3108) provides this function. since some applications do not want to have the added delay of up to two ds1 frames for slip buffering (e.g. tr-496 objective 3-6)), a modified version of byte-synchronous mapping is provided where lrclkn and rsyncn are inputs for floating vt1.5/tu-11 mode. on the tributary or ds1 line side it operates from the input timing block, where data is fed into the block. on the system side it operates off of telecom bus sonet/sdh drop timing. ds1 line side clock and multi-frame synchronization uses the buffering supplied by this block. if the input buffer becomes too full the synchronizer requests a pointer decrement to be generated by the vt ter- mination block which aligns the virtual container to the virtual tributary; this will cause an extra byte of data to be read out of the input buffer in a 500 microsecond period. in figure 2 the v3 byte will be skipped and every- thing will shift up one byte. likewise, if the input buffer is too empty the synchronizer requests a pointer incre- ment causing the v3 position to be repeated and one less byte of data will be read out of the input buffer in a 500 microsecond period. buffer overflow/underflow is a fault condition of the input caused by the loss of frame - 58 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers synchronization (if control bit lof2vais (bit 5) in register x+01h is set to a 1) for this mode. this condition will be passed to the microprocessor interface as an alarm (map error). status bit mps (bit 4) in register x+10h indicates the map error status; mask mpm, latched event mpe, performance value mppm and hard fault value mpfm are all bit 4 of registers x+08h, x+14h, x+18h and x+1ch respectively. rsyncn input defines the start of the first of six vt superframes (the p 1 /p 0 pattern goes from 11 to 00), as shown in the table below. the mapper takes the output of the synchronizer and adds the overhead bits and bytes to it. the o, j2, z6 and z7 positions are driven with the values stored in registers x+36h (o-bits), x+37h (j2 byte), x+38h (z6/n2 byte) and x+39h (z7/k4 byte). for asynchronous operation only, the eight o-bits and six c 1 and c 2 bits are included as shown in figure 2. for byte-synchronous operation the mapper also multiplexes into the payload the data from the rx signaling store, which contains both the abcd signaling bits for each ds0 and also the ds1 sf or esf frame bits. since the signaling and framing bits in a framed ds1 take 3.0 milliseconds for a single esf superframe, six 500-microsecond vt superframes are required to define it. the p 1 /p 0 bits for the byte-synchronous mapping are coded to identify the signaling and framing bits as shown in the table below. refer to figure 2 for the signaling and p 1 /p 0 bit positions. the signaling bits are shown for esf; for sf or esf with four-state signaling the cndn bits are the anbn bits repeated; for two-state signaling anbncndn becomes anananan in the table below. whether the frame bits are provided or not, the t1mx28 can be set to calculate crc-6 over the ds0s only, inserting them in the crc positions in the table below if control bit crc6 (bit 4) in register x+01h is set to a 1. the transwitch t1fx8 (txc-03108) supports the insertion of specific abcd signaling codes for ds0 ais and ds0 rai via control bit operation or signaling buffer write capability, and it optionally forces the robbed bit positions to all 1 to support byte-synchronous gr-253-core signaling conditional requirements. - 59 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers pointer generation and telecom bus slot selection in the t1mx28 device only the vt1.5/tu-11 termination is provided. the vt termination block accepts data, alarms and timing information from the synchronizer/mapper block and completes the generation of the vt1.5/ tu-11 started in the synchronizer/mapper block. signaling and frame bit assignments for byte-synchronous modes p 1 p 0 s 1 s 2 s 3 s 4 f for sf f for esf time (ms) 0 0 a1 a2 a3 a4 f t1 m 1 0.125 0 0 a5 a6 a7 a8 f s1 crc 1 0.250 0 0 a9 a10 a11 a12 f t2 m 2 0.375 0 0 a13 a14 a15 a16 f s2 fps 1 0.500 0 0 a17 a18 a19 a20 f t3 m 3 0 0 a21 a22 a23 a24 f s3 crc 2 0 1 b1 b2 b3 b4 f t4 m 4 0 1 b5 b6 b7 b8 f s4 fps 2 1.000 0 1 b9 b10 b11 b12 f t5 m 5 0 1 b13 b14 b15 b16 f s5 crc 3 0 1 b17 b18 b19 b20 f t6 m 6 0 1 b21 b22 b23 b24 f s6 fps 3 1.500 1 0 c1 c2 c3 c4 f t1 m 7 1 0 c5 c6 c7 c8 f s1 crc 4 1 0 c9 c10 c11 c12 f t2 m 8 1 0 c13 c14 c15 c16 f s2 fps 4 2.000 1 0 c17 c18 c19 c20 f t3 m 9 1 0 c21 c22 c23 c24 f s3 crc 5 1 1 d1 d2 d3 d4 f t4 m 10 1 1 d5 d6 d7 d8 f s4 fps 5 2.500 1 1 d9 d10 d11 d12 f t5 m 11 1 1 d13 d14 d15 d16 f s5 crc 6 1 1 d17 d18 d19 d20 f t6 m 12 1 1 d21 d22 d23 d24 f s6 fps 5 3.000 legend: an, bn, cn, and dn are the signaling bits for 16-state signaling in esf format and represent the bits robbed from ds0 ? n ? in frames 6, 12, 18 and 24. for 4-state signaling cn and dn are interpreted as an and bn. for 2-state signaling bn, cn and dn are interpreted as an. f tn are the frame alignment bits for sf; f sn are the signaling framing bits for sf. fps n are the esf frame alignment bits; crc n are the crc-6 bits in esf; m n are the facility data link bits in esf. - 60 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers each mapper can add its vt1.5/tu-11 to any one of 28 or 84 slots as shown in figure 37 and figure 38 below. control bit tbtval (bit 7) in register x+05h must be set to a 1 for the vt1.5/tu-11 to be added to the telecom bus. bits 6-5 of the same register determine the sts-1, au3 or tug-3 number (one of three). bits 4-2 in this same register determine the vt group or tug-2 number (one of seven) and bits 1 and 0 determine the vt1.5 or tu-11 number (one of four). for asynchronous operation a fixed position for v5 is generated (offset of 78 with a valid v1 and v2; next vt/ tu byte after v1) as shown in figure 2. for the modified version of byte-synchronous operation, the vt syn- chronous payload envelope or virtual container (vt-spe/vc) moves to accommodate frequency differences as described above. the vt termination block provides a pointer generation state machine that follows the bellcore, ansi and itu rules in t1.105, gr-253-core and g.709 by generating no more than a single move- ment every four vt superframes (2.0 ms). loss of frame or signal will cause a new start of vt superframe posi- tion when the signal recovers; this will force a new data flag (ndf) request of the vt termination block. on exiting ais the synchronizer block will re-center its buffer and request an ndf. the synchronizer block will also look for a change in the expected position of rsyncn and indicate an ndf request upstream. valid v1 and v2 bytes are always generated. v3 is used as a stuff opportunity when pointer decrements are done and v4 is unused. for true byte-synchronous operation a fixed position for v5 results from the fact that clock and frame synchronization are outputs which are synchronous with the sonet/sdh structure even though the pointer generation state machine is enabled. two four-bit counters (one to count increments generated and one to count decrements generated) are provided to track frequency deviations. these counters are located at x+25h (bits 7-4 for increment and bits 3-0 for decrement) with latched shadow values located in the same bits at x+2dh. if an overflow of either counter occurs, status bit pgos (bit 1) in register x+10h is set to a 1 and an interrupt can be generated; one second polling/clearing of this counter is recommended. a mask pgom, latched event pgoe, performance value pgopm and hard fault value pgofm are all bit 1 of registers x+08h, x+14h, x+18h and x+1ch respectively. the v5 byte is generated for all modes. v5 is formed from a bit-interleaved parity calculation, a signal label stored in register x+07h bits 2-0, and three alarm bits, rei-v, rfi-v and rdi-v. now that the entire virtual con- tainer is formed, the bip-2 bits are calculated and inserted in the v5 byte as shown in figure 2 based on the previous vt-spe/vc; the msb is chosen to make the sum of the odd bits of every byte in the vt-spe even par- ity and the second bit is chosen to make the sum of all the even bits of every byte in the vt-spe even. the alarm bits are mapped based on the results of demapping, ds1 line conditions or via the ring port as shown in the table below. when the ring port is enabled, v5 only gets rei-v and rdi-v from this port. rfi-v is used in byte-synchronous modes only and comes from a microprocessor-forced value as the result of software- based failure detection (usually in the 2 to 3 second range) of a persisting line, section or high or low order path defect or via the signaling highway as the result of a ds1 rai or yellow alarm. - 61 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers to support three-bit rdi, the z7 byte is also encoded based on different demap conditions or on the three-bit rdi values supplied by the ring port. the unused bits in z7/k4 are supplied from the auxiliary port or the internal register at x+39h; figure 2 shows the z7 byte usage for three-bit rdi. the table below defines the conditions that generate three-bit rdi. when the alarms occur in the demap side of the t1mx28 and are sup- plied internally or via the ring port, the higher priority code always replaces the lower priority code. vt/tu idle and ais insertion are performed at this point. microprocessor interface controls for v5 allow either a valid v5 with an all-zeros payload to be generated for idle or an all-zeros v5 for unequipped. control bit idle (bit 7) in register x+00h, when set to a 0, powers down the channel. control bits rdiis, febeis, sbipe, v5 generation alarm sources and controls alarm microproc. force demap conditions ds1 line conditions enable controls ring bit ring enable bip-2 sbipe = 1, reg. x+03h, bit 5. ectl7p-ectl0p in reg. 01dh sets number of times none none febeis = 1, reg. x+02h, bit 1, enables microproc. forcing. febeis = 0 for nor- mal calculation. none none rei-v = 1 sfebe = 1, reg. x+03h, bit 5. ectl7p-ectl0p in reg. 01dh sets number of times one or two bip-2 errors none febeis = 1, reg. x+02h, bit 1, enables microproc. forcing. febeis = 0 for nor- mal calculation. rei-v = 1 ringen = 1, reg. x+0bh, bit 4 rfi-v = 1 srfi = 1, reg. x+03h, bit 1. software integrated failure state from los, lof, ais-l/p/ v, lop-p/v, uneq- p/v, & plm-p/v yellow via signaling highway; y-bit = 1 yel2rfi = 1, reg. x+01h, bit 1. none none rdi-v = 1 srdi-vsd = 1, reg. x+02h, bit 6. ais-v, lop-v none rdiis = 1 reg. x+02h, bit 3 enables microproc. forcing. rdiis = 0 for normal insertion from demap. rdi-vsd = 1 ringen = 1 reg. x+0bh, bit 4 srdi-vcd = 1, reg. x+02h, bit 5. uneq-v rdi-vcd = 1 z7 three-bit rdi generation sources and controls alarm microproc. force demap conditions z7 code bits 5, 6, 7 priority enable controls ring bit ring enable rdi-vsd = 1 srdi-vsd = 1, reg. x+02h, bit 6. ais-v, lop-v 101 1 rdiis = 1, reg. x+02h, bit 3 enables microproc. forcing. rdiis = 0 for normal insertion from demap rdi-vsd = 1 ringen = 1, reg. x+0bh, bit 4 rdi-vcd = 1 srdi-vcd = 1, reg. x+02h, bit 5. uneq-v 110 2 rdi-vcd = 1 rdi-vpd = 1 srdi-vpd = 1, reg. x+02h, bit 7. plm-v 010 3 rdi-vpd = 1 none none no defects 001 4 all 0 - 62 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers sfebe, transmit signal label, srdi-vpd, srdi-vsd, srdi-vcd and tx z7 all have an effect on the idle sig- nal sent. the table below provides recommended settings for idle and unassigned (but still monitored) and idle but unequipped (not monitored). note: x=don ? t care control bits sh2vais, los2ais, lof2vais, ais2vais, sdaiss and svtais, together with the mapping mode control bits (mode1, mode0 and datacom) and the line decoder controls (encod and explos) deter- mine whether ais or vt ais is mapped. the ais alarm bits on the signaling highway, loss of frame in modi- fied byte-synchronous mode, microprocessor command, an all-ones detected in the decoder, a los condition detected in the decoder and the los condition via a signal on the lais lead can be used to generate an ais (ds1 payload all-ones will be mapped in place of the received signal) or vt ais (payload, overhead and v1 plus v2 bytes all-ones). the table below details the feature. idle control of t1mx28 control bit valid v5 & z7 payload = 0 payload z7 & v5 = 0 idle; reg. x+00h, bit 7 0 0 rdiis; reg. x+02h, bit 3 0 1 srdi-vpd; reg. x+02h, bit 7 x 0 srdi-vsd; reg. x+02h, bit 6 x 0 srdi-vcd; reg. x+02h, bit 5 x 0 febeis; reg. x+02h, bit 1 0 1 sfebe; reg. x+03h, bit 7 0 0 sbipe; reg. x+03h, bit 5 0 0 tx z7; reg. x+39h, bits 7-0 00h 00h ringen (if ring port used); reg. x+0bh, bit 4 1 0 - 63 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers note: x=don ? t care vt/tu pointer tracking and telecom bus slot selection in the t1mx28 device only the vt1.5/tu-11 termination is provided. the vt termination block accepts data, high order alarms and timing information from the telecom bus interface block, tracks the vt1.5/tu-11 pointer and extracts the alarms. the vt termination block also provides data, alarms and control to the desynchro- nizer/demapper block. all operations (pointer interpretation, pointer generation, vt/tu lop detection, vt/tu ais detection, etc.) are performed in accordance with gr-253-core, g.709, and g.783. each mapper can drop its vt1.5/tu-11 from any one of 28 or 84 slots as shown in figure 37 and figure 38 below. control bit tbrval (bit 7) in register x+04h must be set to a 1 for the vt1.5/tu-11 to be dropped from the telecom bus. bits 6-5 of the same register determine the sts-1, au3 or tug-3 number (one of three). bits 4-2 in this same register determine the vt group or tug-2 number (one of seven) and bits 1 and 0 determine the vt1.5 or tu-11 number (one of four). the values chosen may be the same or different from the add bus values. the starting location of the v1 byte is determined by the v1 pulses in the adc1j1v1(bdc1j1v1) signals. the vt/tu pointer bit assignment for the v1 and v2 bytes is shown below. the alignment is necessary to deter- mine the starting locations of the v5 byte and the other bytes that are carrying the 1544 kbit/s format. ais and vt-ais generation sources and controls alarm generated microproc. force ds1line conditions mode1 reg. x+00h, bit 1 mode0 reg. x+00h, bit 0 datacom reg. x+00h, bit 5 enable controls ds1 ais sdaiss = 1, reg. x+03h, bit 6 all-ones x x x none (passes through) any x x x none lais lead high 0 x x explos =1, reg. x+00h, bit 6 & los2ais = 1, reg. x+01h, bit 6 los detected 0 x x encod = 1, reg. x+00h, bit 2 & los2ais = 1, reg. x+01h, bit 6 vt ais svtais = 1, reg. x+03h, bit 0 any x x x none lais lead high 1 x x explos =1, reg. x+00h, bit 6 & los2ais = 1, reg. x+01h, bit 6 tsigln a-bits = 1 1 x 0 sh2vais = 1, reg. x+01h, bit 7 >99.9% ones detected in decoder 1 x 0 ais2vais = 1, reg. x+01h, bit 0 loss of signal on rsyncn 1 1 x lof2vais = 1, reg. x+01h, bit 5 - 64 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers i = increment bit d = decrement bit n = new data flag bit (enabled = 1001 or 0001/1101/1011/1000, normal or disabled = 0110 or 1110/0010/0100/0111) negative justification: inverted 5 d-bits and accept 8 out of 10 rule positive justification: inverted 5 i-bits and accept 8 out of 10 rule ss-bits (vt size) = 11 for 1544 kbit/s, pointer bytes bit assignment the pointer value is a binary number with a range of 0 to 103 for the 1544 kbit/s format. it indicates the offset from the v2 byte to the first byte in the vt1.5 mapping. the pointer bytes are not counted in the offset calcula- tion. the pointer offset arrangement for this format is shown below. vt/tu pointer offset locations v1 byte v2 byte 1234567812345678 nnnnss-bits ididididid v1 78 79-102 103 v2 0 1-24 25 v3 26 27-50 51 v4 52 53-76 77 1544 kbit/s tu-11/vt1.5 - 65 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers twenty-eight independent pointer tracking state machines are used in the t1mx28. the pointer tracking algo- rithm is illustrated in figure 26. the pointer tracking state machine is based on the pointer tracking machine found in the latest etsi requirements, and is also valid for both bellcore and ansi. see gr-253-core and g.709 for pointer processing rules. where differences occur the gr-253-core rules are used; in particular, the ais state is not exited to lop state on invalid pointers; receipt of all-ones for a pointer is considered an invalid pointer until 3 consecutive all-ones pointers are received (considered as ais); new pointers without ndf count toward the 3 consecutive new pointers even though an inc/dec action is taken as the result of the new pointer mimicking an inc/dec; the inc/dec decision is 8 out of 10 bits. when control bit sdhp (bit 5) in register 007h is set to a 1, the transition from ais to lop is enabled (shown dotted), which is required in itu recommendations. increments and decrements are forwarded to the desynchronizer for counting and use in pointer leak controls as described below. figure 26. vt/tu pointer tracking state machine inc lop ais dec norm 3 x ais_ind (offset undefined) 3 x new_point (accept new offset) 3 x ais_ind (offset undefined) 3 x new_point (accept new offset) 3 x any_point dec_ind (decr. offset) 3 x new_point (accept new offset) 3 x new_point (accept new offset) 3 x any_point ndf_enable (accept new offset) 8 x inv_point (offset undefined) 3 x new_point (accept new offset) 3 x ais_ind (offset undefined) 8 x inv_point (offset undefined) ndf_enable (accept new offset) 3 x ais_ind (offset undefined) 8 x ndf_enable (offset undefined) ndf_enable (accept new offset) ndf_enable (accept new offset) ndf_enable (accept new offset) 3 x new_point (accept new offset) 3 x any_point inc_ind (incr. offset) 3 x ais_ind (offset undefined) ndf - 66 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers from the telecom bus input, v1 and v2 are extracted by means of adc1j1v1(bdc1j1v1) and adspe(bdspe). vt/tu lop and vt/tu ais are individually made available to the microprocessor interface as status bits vaiss and lops (bits 5 and 4) in register x+11h. masks vaism and lopm, latched events vaise and lope, performance values vaispm and loppm and hard fault values vaisfm and lopfm are all bits 5 and 4 of registers x+09h, x+15h, x+19h and x+1dh respectively. the logical ? or ? of these two alarms is handled as ais for the demapped ds1 as described above in the transmit data and signaling highway sec- tion. the ? ss ? bits are compared to the expected value of ? 11 ? for a vt1.5/tu-11 and are interpreted as lop (high level signal failure input at leads adfail(bdfail) masks vtais, vtlop and signal label mismatch). the ss-bits are available as status only bits rxss1 and rxss0 (bits 4 and 3) in register x+20h. the demapper the signal label received in the v5 byte is extracted and sent to the microprocessor interface. it is stored in bits 2-0 of register x+20h. additional processing is performed to detect a signal label mismatch (compare with expected signal label) and the unequipped code. both conditions are reported to the microprocessor interface and notification of an unequipped or signal label mismatch condition (also known as vt path label mismatch or plm-v) is handled as described herein for the mapping direction. status bits unes and slms (bits 2 and 1) in register x+11 indicate the current condition. masks unem and slmm, latched events unee and slme, performance values unepm and slmpm and hard fault values unefm and slmfm are all bits 2 and 1 of registers x+09h, x+15h, x+19h and x+1dh respectively. a mismatch alarm is considered as 5 con- secutive signal labels of a different condition; 5 consecutive matches will clear the alarm. the signal label ? equipped - nonspecific ? (001) received is not considered a mismatch to any non-zero expected value. also, if the expected signal label is set to 'equipped-nonspecific' (001) any non-zero value received for the signal label will not cause an alarm. if an unequipped signal label is received, the t1mx28 will generate an alarm regardless of the setting of the expected signal label (including 000). the alarm should be masked when both ends of a connection are programmed unequipped but a path exists. the table below shows the alarms based on the received versus expected value, per gr-253-core. the v5 and z7/k4 bytes are further processed to extract bip-2 errors, vt/tu rei (febe) events, and vt/tu rdi-v and vt/tu rfi alarms. vt/tu rdi-v is de-bounced for 5 (default) or 10 (selectable) consecutive vt superframes before an alarm is declared; 5 (default) or 10 (selectable) consecutive rdi-v = 0 will clear the alarm. de-bounce control is through global register rdid10p (bit 0) in register 01eh which, when set to a 1, causes the t1mx28 to de-bounce all rdi bits over 10 vt superframes. rfi is de-bounced for 10 consecutive vt superframes before an alarm is declared; 10 consecutive rfi = 0 will clear the alarm. v5 byte rdi and rfi signal label mismatch and unequipped alarms expected signal label stored in reg. x+07h, bits 6-4 received signal label 000 001 010 011 100 101 110 111 000 * m uneq 001 m m 010 m plm 011 plm m plm 100 plm m plm 101 plm m plm 110 plm m plm 111 plm m legend: m = match found and no alarm plm = path label mismatch and alarm, plm-v uneq = unequipped alarm (* t1mx28 will generate an alarm for rx/exp=000/000) - 67 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers alarms are sent to the microprocessor interface once de-bounced, with status bits rfis and rdi-vs (bits 3 and 0) in register x+11h. masks rfim and rdi-vm, latched events rfie and rdi-ve, performance values rfipm and rdi-vpm and hard fault values rfifm and rdi-vfm are all bits 3 and 0 of registers x+09h, x+15h, x+19h and x+1dh respectively. the vt/tu rfi alarm can be sent to the signaling highway as a ds1 yellow for byte-synchronous modes only, as was described in the transmit data and signaling highway sec- tion. bip-2 errors and vt/tu rei (febe) events are accumulated in 12-bit overflow indicating counters. control bit sdhp (bit 5) in register 007h, when set to a 1, will cause bip-2 errors to count in blocks (count 1 error if one or both bip-2 bits received is different than calculated). when sdhp is set to a 0 each different bit counts as an error. the bip-2 error counter is located at location x+26h and x+27h with a shadow value located at x+2eh and x+2fh. an overflow bit bipos (bit 6) in register x+11h is set to a 1 if an overflow occurs. the rei (febe) error counter is located at location x+28h and x+29h with a shadow value located at x+30h and x+31h. an overflow bit feos (bit 7) in register x+11h is set to a 1 if an overflow occurs. masks bipom and feom, latched events bipoe and feoe, performance values bipopm and feopm and hard fault values bipofm and feofm are all bits 6 and 7 of registers x+09h, x+15h, x+19h and x+1dh respectively. the t1mx28 supports three-bit rdi using the z7/k4 byte. three-bit rdi is an enhanced remote defect indica- tion that provides three classes of defects: payload defect (path label mismatch), server defects (loss of pointer or ais) and connectivity defects (unequipped). the mechanism uses a combination of v5 bit 0, and z7/k4 bits 3, 2 and 1 to implement an algorithm that is compatible with the existing rdi-v (v5 bit 0) and the new indications. when z7/r4 bits 2 and 1 = 00 or 11, the rdi is from old equipment. when z7/k4 bits 2 and 1 = 01 or 10, the rdi is from enhanced equipment. enhanced rdi is checked for persistency for either 5 or 10 consecutive vt superframes, the same as for rdi-v. alarms are available to the microprocessor interface. sta- tus bits rdi-vpds, rdi-vsds and rdi-vcds (bits 2-0) of register x+12h indicate the signals received in z7/ k4. masks rdi-vpdm, rdi-vsdm and rdi-vcdm, latched events rdi-vpde, rdi-vsde and rdi-vcde, performance values rdi-vpdpm, rdi-vsdpm and rdi-vcdpm and hard fault values rdi-vpdfm, rdi- vsdfm and rdi-vcdfm are all bits 2 through 0 of registers x+0ah, x+16h, x+1ah and x+1eh respectively. the table below indicates the v5 and z7/k4 bit settings the t1mx28 uses to support both old equipment and enhanced equipment. higher priority events (e.g., ais) cause rdi codes to be sent that override lower priority rdi codes when both conditions occur simultaneously. the signal failure input leads, adfail(bdfail), blocks all rdi-v detection. the t1mx28 will automatically switch between single-bit and three-bit rdi based on the received z7/k4 bits 2 and 1. rdi-v bit settings and interpretation notes: a. these codes are transmitted by equipment that does not support enhanced rdi-v. if enhanced rdi-v is not supported, z7 bits 6 and 7 must be set to the same value. b. a signal label mismatch (plm-v) does not cause a one-bit rdi-v c. this code is transmitted by equipment that supports enhanced rdi-v. d. v5 bit 8 is set to the same value as z7/k4 bit 5 by the equipment that supports enhanced rdi-v. at the receiving equipment, v5 bit 8 is ignored unless z7 bits 6 and 7 are both set to ? 0 ? or both set to ? 1 ? . z7/k4 bits 5, 6 and 7 v5 bit 8 priority of enhanced rdi-v codes trigger interpretation yxx a 0 not applicable no defects no rdi-v defect yxx a 1 not applicable ais-v, lop-v, uneq-v b rdi-v defect (one-bit rdi-v) 001 c 0 d 4 no defects no rdi-v defect 010 c 0 d 3 plm-v rdi-v payload defect 101 c 1 d 1 ais-v, lop-v rdi-v server defect 110 c 1 d 2 uneq-v rdi-v connectivity defect - 68 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers the signal label expected and the signal label to be sent in the v5 by the t1mx28 are stored separately in register x+07h. acceptable values for the signal label are as shown in the following table: desynchronization and pointer leak rate calculations desynchronization is performed in two stages, a pointer leak buffer and a dpll/fifo. thus the t1mx28 removes jitter from the demapped and destuffed vt1.5 or tu-11 in two steps. first the payload is sent to a pointer leak buffer which is a 10-byte deep fifo centered at 5 bytes, allowing for up to 5 vt pointer increments or decrements in a row to be absorbed when a change in a network condition or rate adjustment for byte-syn- chronous mappings are translated into vt pointer movements. the pointer leak buffer converts vt pointer movements ( 8 bits) into slowly leaked single 1 bit adjustments to the dpll/fifo. the pointer leak buffer can be programmed to leak in steps of 8 milliseconds per bit. for test purposes, the pointer leak buffer may be bypassed by setting control bit byplbp (bit 4) in register 03dh to a 1. sts-1 pointer movements have approx- imately one twenty-eighth of the effect of a vt pointer movement; sts-1 pointer movements, in effect, repre- sent about one half of a stuffing bit and are handled by the dpll in the same way as a stuffing bit. the second filtering stage is provided by the dpll, which operates from the ? 31.5 times 1.544 mhz ? clock (48.636 mhz) supplied to lead srclk. the dpll controls a fifo whose depth measurement is made once every vt superframe. from the depth measurement the dpll adjusts its output frequency to match the effects of stuffing performed for asynchronous mapping and pointer movements which have been converted to stuffing by the pointer leak buffer. the dpll provides rate adjustments for byte-synchronous mappings as well as rate adjustments affecting both mappings in addition to asynchronous rate tracking. the dpll has a single pole low pass filter characteristic with a 1.8 hz corner frequency. residual jitter without pointer movement of the demapper is approximately 0.20 ui peak to peak (p-p). mapping and demapping jitter combined with vt pointer movements is under 1.20 ui p-p. through delay (da1 to or from telecom bus) is under 65 s. for testing purposes the dpll can have its output frequency locked by setting control bit dpllk (bit 7) in glo- bal register 03ch to a 1; control bits dpll6p-dpll0p in the same global register are used to adjust the output frequency; this affects all twenty-eight channels. when control bit dpllk is set to a 0, control bits dpll6p- dpll0p can be used to change the dpll bias offset which changes the dpll fifo ? s residual depth. control register 03ch must be set to 00h for normal desynchronizer operation. since a wide range of vt pointer increment and decrement rates can occur, the t1mx28 provides a wide range of leak rates. as was mentioned above, the pointer increments and decrements received represent a variety of sources of frequency correction relative to the sonet or sdh clock rates that can occur after a ds1 signal is mapped asynchronously (e.g., due to synchronization failures or clock noise) as well as part of the mapping function for a byte-synchronously mapped ds1. a vt pointer movement represents an 8-bit instantaneous fre- quency correction (an 8 ui jitter spike). such adjustments are not palatable to most traditional ds1 network equipment and may cause slips or bit errors. the t1mx28 has a programmable pointer leak buffer that can be set to convert the received vt pointer movements to a rate that can match the actual ds1 payload frequency. for example, if a pointer decrement is being received once every second, the ds1 payload signal needs to be adjusted 8 hz higher. by programming the pointer leak buffer to leak one bit every 125 milliseconds, the dpll will automatically run 8 hz faster continuously by receiving an extra bit in its fifo every 125 milliseconds. if the pointer leak rate is set too slow the pointers will build up in the pointer leak buffer; at a 12 bit (one and a half pointers) level the pointer leak rate automatically doubles to compensate. if the pointer leak rate is set too fast the frequency will be over-corrected for a period and then return to nominal. for example, if the pointer leak rate were set to once every 63 milliseconds for the ? pointer decrement per second ? case, the output frequency vt/tu assignment v5 signal label (bits 5-7) idle/unequipped 000 equipped - nonspecific 001 asynchronous mapping 010 byte-synchronous mapping 100 - 69 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers would run 16 hz faster (8 hz too high) for one half second and return to nominal (8 hz too low) for one half sec- ond. this would cause a frequency modulation of the ds1 output signal that would result in jitter and wander. the mean time interval error (mtie) would build up to an undesirable level relative to gr-253-core objec- tives and requirements. the table below indicates the pointer leak rate range available by setting per channel control bits pl8-pl1 in register x+06h. a software-based control loop is required to program the t1mx28 to meet mtie requirements. the control loop is required to read the received pointer increment and decrement counters, bits 7-4 in register x+24h and bits 3-0 in register x+24h respectively for unlatched values; if the one second performance feature is used by set- ting control bit enpmfmp (bit 3) in register 006h to a 1 and supplying a 1 hz 32 ppm clock on lead t1si, latch pointer increment and decrement values are preferably used from bits 7-4 in register x+2ch and bits 3-0 in register x+2ch respectively. measuring the 4-bit counters every one second is sufficient for up to 15 incre- ments or decrements, representing up to 120 hz, which is beyond the range of a byte-synchronous ds1 used as a clock source (lrclkn as an input) handled between two add/drop multiplexers experiencing a syn- chronization failure. to initialize the pointer leak buffer, set it to the maximum expected or possible leak rate required from the application (asynchronous, byte-synchronous, network clock stratum references along the path, etc.). the table below provides some typical settings. from the values that are read, use the net value (increment less decrement) to form a running average over a 30 second period. this value is used to calculate the nearest applicable pointer leak rate for within 12 bits of center and written to the t1mx28 pl8-pl1 per channel control bits. at each subsequent one-second period, the oldest value is discarded and the newest value is added; the pointer leak rate is again calculated and written to the t1mx28 pl8-pl1 control bits. for a constant stream of pointer increments or decrements, the last pointer should be leaked out just before the next pointer arrives. missing or additional pointer increments or decrements in the stream will alter the average only slightly. figure 27 below shows the general algorithm. each time a t1mx28 is reset, or the channel experiences an ais, lop, ndf or los, the algorithm needs to be restarted. the algorithm is independent for all twenty-eight channels and must be performed as such. the maximum range of adjustment due to pointers is when pl8-pl1 is set to 00h. with at least one and a half residual increments or decrements, one additional or less than normal bit per 8 milliseconds will be sent to the dpll representing 125 hz. this range supports byte-synchronous mapping for ds1 signals which are 50 hz. pl8 - pl1 time between bits leaked from pointer leak buffer when less than 12 bits from center time between bits leaked from pointer leak buffer when equal to or more than 12 bits from center 00h 16 ms 8 ms 01h 32 ms 16 ms 02h 48 ms 24 ms fdh 4,064 ms 2,032 ms feh 4,080 ms 2,040 ms ffh 4,096 ms 2,048 ms mapping application clock difference pl8 - pl1 asynchronous add drop mux to dcs 38 hz [20 ppm +4.6 ppm] 01h byte-synchronous: lrclkn an output add drop mux to dcs 38 hz [20 ppm +4.6 ppm] 01h byte-synchronous: lrclkn an input add drop mux to dcs with customer ds1 87 hz [20 ppm +4.6 ppm + 32 ppm (ds1 @ stratum 4)] 00h asynchronous dcs to dcs, one stratum 2 7.1 hz [4.6 ppm] 08h asynchronous dcs to dcs, both stratum 3 14.2 hz [9.2 ppm] 04h - 70 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 27. pointer leak rate algorithm set fifo leak rate to 01 hex (note 3) measure 1 second, add to sum (notes 4, 5) not 30 seconds 30 seconds calculate fifo leak rate (note 5) start from power on, vtais, vtlop, or higher order path or set fifo leak rate (note 6) measure 1 second (note 6) subtract oldest and add newest (note 7) notes: 1. the procedure described must be performed independently for each of the twenty - eight channels. 2. the procedure shown uses a 30 second sliding window with a 1 second resolution. 3. the initial leak rate is application dependent; however setting the pl8 - pl1 value in registers x06h to 01h will cover all asynchronous applications and setting it to 00h will cover all byte synchronous appli- cations where the ds1 line supplies clock (pleisiochronous). 4. measure 30 consecutive one-second samples from the receive pointer increment and decrement counters. if the counters overflow use a value of 16 for the overflowed counter: s 1 = pointer increment value - pointer decrement value for first one second. s 2 = pointer increment value - pointer decrement value for second one second and so on. s 30 = pointer increment value - pointer decrement value for thirtieth second. 5. calculate the leak rate: leak rate = the smaller of (hex[int{234/c}], hex[int{34/d}] if d > 2, hex[int{25/e}] if e > 2, hex[int{17/f}] if f > 2, hex[int{8/g}] if g > 2) where hex is the hexadecimal value, int is the integer value: c = absolute value [sum(s i to s 30+i )], d = absolute value [sum(s 27+i to s 30+i )], e = absolute value [sum(s 28+i to s 30+i )], f = absolute value [s 29+i + s 30+i ], g = absolute value [s 30+i ] and i represents the number of times through the loop above (notes 5, 6 and 7). if the c is 0 set the leak rate to ffh. a pointer will be leaked before another arrives for uniform pointer arrivals for 0 < c < 234 arrival rates. if d, e, f, or g > 2, faster pointer leaking accounts for a rapid change in pointer arrival rate (e.g. start up after a cool down sequence). 6. set the leak rate register between 1 and 255 per note 5, and take another measurement (e.g., s 31 ). 7. recalculate the value of c, d, e, f and g in note 5 by discarding the oldest value and adding the newest value; (i = i + 1). 8. continue the loop in notes 5, 6 and 7 until the low order path is disrupted (e.g., vtais, vtlop, reset or higher order path failure like lop, ais). line los, ais, lop or reset, etc. - 71 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers in general, the receive dpll/fifo in the desynchronizer should never overflow or underflow. if it does it will set status bit dmps (bit 6) in register x+10h and recenter the fifo. mask dmpm, latched event dmpe, perfor- mance value dmppm and hard fault value dmpfm are all bit 6 of registers x+08h, x+14h, x+18h and x+1ch respectively. jitter measurements equipment used in t1mx28 jitter measurements: - hewlett packard digital transmission analyzer, hp-3784a - anritsu stm/sonet analyzer, mp1560a - t1mx28 test fixture jitter tolerance test input jitter tolerance is defined in [gr-499] section 7.3.1 as: the minimum amplitude of sinusoidal jitter at a given frequency that, when modulating the signal at an equipment input port, results in more than 2 errored seconds in a 30-second measurement interval. the jitter tolerance is measured by injecting jitter at various frequencies into the t1mx28 ? s ds1 port by using the hp-3784a as shown in figure 28. the vt1.5 (tu11) mapped data will be monitored on the sonet/sdh side by using the anritsu mp1560a. the jitter tolerance limit of the device is the amount of jit- ter insertion allowed before a bit error is detected at the point where data is being added to the sonet/ sdh data stream. figure 29 shows the jitter tolerance requirements and the measured results for the t1mx28 device. figure 28. jitter tolerance test setup mp 1560a t1mx28 hp-3784a 1.544 mbit/s ds1 interface stm/sonet analyzer test fixture digital transmission analyzer sonet data - 72 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 29. jitter tolerance measurements jitter transfer test for this test the hp-3784a is used to inject a fixed jitter level (1.0 ui) into the ds1 interface of the t1mx28, as shown in figure 30. the mapped ds1 data is then looped back at the sonet/sdh interface and dropped by the same device. the dropped ds1 jitter is measured at the hp-3784a using a filter of 10hz - 40 khz. the actual jitter transfer measurements are for the t1mx28 device are shown in figure 31. input jitter frequency requirement (ui pp) maximum input jitter (ui pp) f1 10 hz > 5.0 12.0 100 hz > 5.0 7.5 f2 500 hz > 5.0 11.8 1 khz > 1.9 11.5 f3 8 khz > 0.1 11.0 20 khz > 0.1 3.9 f4 40 khz > 0.1 1.9 0.1 1 10 100 10 100 1000 10000 100000 input jitter frequency (hz) input jitter amplitude (ui-pp) maximum tolerated input jitter minimum requirement [gr499] sec. 7.3.1 - 73 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 30. jitter transfer test setup figure 31. jitter transfer measurements input jitter filter used measured output jitter (ui) frequency (hz) unit interval (ui) 10 1.0 (f1 - f4) 0.176 50 1.0 (10 hz -> 40 khz) 0.070 100 1.0 0.052 200 1.0 0.058 600 1.0 0.082 1000 1.0 0.119 hp-3784a test fixture digital transmission analyzer t1mx28 0.01 0.1 1 10 10 100 1000 input jitter frequency (hz) ui input measured output - 74 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers jitter generation the setup shown in figure 32 was used for both the mapping and combined jitter measurements described below. figure 32. jitter generation test setup mapping jitter measurement the following table lists the mapping jitter measurements made with the test setup shown in figure 32 in the absence of sts or vt(tu) pointer adjustments. notes: 1. per recommendation g.783 (04/97). 2. per bellcore gr-253-core issue 2 dec. 95: rev 2 jan. 99. 3. these values are for further study. interface filter characteristics maximum output jitter (ui pp) requirement measured per g.783 (note 1) per bellcore (note 2) ds1 (f1) (f4) 10 hz -> 40 khz (note 3) 0.7 0.031 (f3) (f4) 10 hz -> 40 khz 0 .1 0.7 0.015 anritsu hp-3784a 1.544 mbit/s ds1 interface stm/sonet analyzer test fixture digital transmission analyzer sonet data mp 1560a t1mx28 - 75 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers combined jitter measurement this table lists the combined jitter measurements made with the test setup shown in figure 32 with sts-1 and vt 1.5 (tu-11) pointer adjustments as indicated in the first column and shown in figure 33. notes: 1. per recommendation itu-t g.783 (04/97). 2. per bellcore gr-253-core issue 2 dec. 95: rev 2 jan. 99. 3. these are values written into the desynchronizer pointer leak rate register for mapper port n (register address x+06). normally the pointer leak rate register is controlled by the external microprocessor through the implementation of the pointer leak rate algorithm shown in figure 27. 4. ao is the mapping jitter generated by the device under test. please see mapping jitter measurement on the previous page. pointer test sequence filter leak rate value (hex) (note 3) maximum output jitter (ui pp) requirement measured g.783 (note 1) bellcore (note 2) single pointer adjustment = 30 s (f1) (f4) 10 hz -> 40 khz 10h 1.5 ao + 0.60 (note 4) 0.22 periodic vt1.5 pointer adjustment (26-1 pattern) = 0.2 s 01h or 02h 1.5 1.3 0.64 periodic vt1.5 pointer adjustment (continuous pattern) = 0.2 s 01h or 02h 1.5 1.3 0.60 periodic vt1.5 pointer adjustment (continuous pattern plus add) = 1 s t = 30 ms 02h 1.5 1.9 0.78 - 76 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 33. standard pointer test sequences measurement period pointer adjustment initialization time 30 s single pointer adjustment test sequence 26 no pointer adjustment start of next 26 - 1 pattern periodic vt1.5 pointer adjustment test sequence (26-1 pattern) periodic vt1.5 pointer adjustment test sequence (continuous pattern) periodic vt1.5 pointer adjustment test sequence (continuous pattern plus add) pointer adjustment added pointer pointer adjustment cool down t - 77 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers microprocessor interface and common control/status i/o the microprocessor interface and common control/status i/o block allows access and control for each of the twenty-eight ds1 mappers. it also provides common control and status of the entire t1mx28. alarm informa- tion detected by the mappers can be read as current status (which may not persist long enough to be easily observed in some cases like counter overflows) and is also latched in event registers which are write to clear. either the arrival or the departure of a condition can be individually enabled to set the event register. to facili- tate either interrupt or polled systems, global interrupt masks, per channel interrupt masks, global event and global polling registers are provided. to assist in the collection of performance parameters, shadow registers and counter latching are provided in addition to latched value and raw value registers. two forms of shadow registers (performance-pm and fault logic-fm) and counter latching are provided at separate locations and are triggered by an external one second clock input lead (t1si), as is described below. the configuration of each mapper is provided by this interface. the serial port control block is also controlled by the microprocessor interface and common control/status i/o. the microprocessor bus supports both intel and motorola style pro- cessors with a minimum amount of interface logic. an external lead (motoi) configures the type of bus sup- ported. the data bus is an 8-bit, bidirectional, 3-state port. the internal control and status registers are accessed through this port. when not accessed, this port is in a high impedance state. the address bus is a 9- bit input port. these address leads select individual control and status registers within each group of seven mappers. selip (p = 1 to 4) are the microprocessor port select signals. seli1 selects the first group of seven mappers (channels 1-7) and seli2 , seli3 and seli4 selects the other three groups of seven mappers. the register locations are repeated for each of the four groups of seven mappers to enable access to all registers or to those specifically selected through the use of the seli p leads. wri and readi / readi/wri are the microprocessor port write and read/write input leads (only the latter is used for the motorola interface). the rdyo/dtacko output is used to delay microprocessor access, if required to access internal registers. the intop/irqop (p = 1 to 4) outputs are the microprocessor port interrupt lines. into1/irqo1 is an interrupt line from the first group of seven mappers (channels 1-7) and into2/irqo2 , into3/irqo3 and into4/irqo4 are interrupt lines from the other three groups of seven mappers. the rsti input is the overall device reset line that resets all counters, state machines and the configuration. pcki is a high speed processor clock input sig- nal that is used by all blocks. alarms the nineteen per channel alarms have been covered in the above sections. to facilitate a quick microprocessor location of an alarm that has been programmed to generate an interrupt, global event and mask registers are provided as well as an activity register. global masks are provided at register locations 015h and 016h. set- ting any of these to a 1 will prevent that condition from generating an interrupt; for example, if the t1mx28 is programmed for asynchronous operation, setting grfimp (bit 3) in register 016h to a 1 would prevent rfi alarms (used in byte-synchronous mappings) from causing spurious interrupts. global event registers are pro- vided at locations 013h and 014h. these registers are the logical ? or ? of all seven like per channel registers; for example, glosep (bit 5) in register 013h is the logical ? or ? of all seven lose per channel event registers. note that grdiep and grdimp provide a global event indication and mask for all rdi conditions (rdi-ve; v5 bit 8 and rdi-vpde, rdi-vsde, rdi-vcde; z7 bits 5, 6 and 7). to facilitate polling, an activity register is provided at location 011h; each bit ch1p to ch7p (bits 0 to 6) represents a mapper channel (1 to 7) for each of the four groups of seven mappers. each bit chnp is the logical ? or ? of all 19 event bits for mapper channel ? n ? . to disable all interrupts to leads intop/irqop , control bit simp (bit 7) in register 006h can be set to a 1; polling may be done instead to detect alarm events. the interrupt polarity may be inverted by setting control bit ipolp (bit 4) in register 006h to a 1. events may be latched into the event registers (global registers 00ch and 00dh or per channel registers x+14h, x+15h and x+16h) either on the onset of the condition, the exit of the condition or both. control bit risep (bit 6) in register 006h, when set to a 1, will cause the associated event bit to be set when a status bit changes from 0 to 1. likewise, control bit fallp (bit 5) in register 006h, when set to a 1, will cause the associated event bit to be set when a status bit changes from 1 to 0. by setting both risep and fallp to a 1, both the onset of an alarm and the clearing of an alarm will cause an interrupt if the event register is cleared after the onset of the alarm. - 78 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers assuming all mask bits are set to a 0, asynchronous mode is used, and both risep and fallp are set to a 1, the following scenario would apply if mapper channel 2 (x=080h) detected a los condition for 2 seconds at its line decoder. first, bit 5 of register 090h (loss) would be set to a 1. bit 5 of register 094h (lose) would be set to a 1 on the rising edge of loss. this would set bit 5 of register 013h (glosep) to a 1, set bit 1 of register 011h (ch2p) to a 1 and cause an interrupt to be asserted on leads intop/irqop . the software in the attached microprocessor would respond by reading registers 011h, 013h and 014h. analysis would indicate an los change at channel 2. the software in the attached microprocessor would then respond by reading reg- isters 090h and 094h, followed by clearing register 094h by writing 00h to it. this writing to clear will automat- ically clear the interrupt, bit 5 of register 013h (glosep) and bit 1 of register 011h (ch2p). at the end of 2 seconds, bit 5 of register 090h (loss) will clear. bit 5 of register 094h (lose) would be set on the falling edge of loss. this would set bit 5 of register 013h (glosep) to a 1, set bit 1 of register 011h (ch2p) to a 1 and cause an interrupt to be asserted on leads intop/irqop . the software in the attached microprocessor would respond by reading registers 011h, 013h and 014h. analysis would indicate an los change at channel 2. the software in the attached microprocessor would then respond by reading registers 090h and 094h followed by clearing register 094h by writing 00h to it. this writing to clear will automatically clear the interrupt, bit 5 of reg- ister 013h (glosep) and bit 1 of register 011h (ch2p). to provide for operational security and fault localization, system clocks and reference signals are optionally monitored for lack of transitions and alarmed to the microprocessor interface and the internal alarm outputs in aiao (for p = 1 and 2) or biao (for p = 3 and 4). status bits tbrcksp, tbrsnsp and tbrpasp (bits 7 through 5) in register 00ah indicate a failure of adclk (for p = 1 and 2) or bdclk (for p = 3 and 4), adc1j1v1 (for p = 1 and 2) or bdc1j1v1 (for p = 3 and 4), or adspe (for p = 1 and 2) or bdspe (for p = 3 and 4), if set to a 1, respectively. mask bits mtbrcfp, mtbrsfp and mtbrpfp, latched event bits tbrckep, tbrsnep and tbrpaep, performance values tbrckpmp, tbrsnpmp and tbrpapmp, and fault values tbrckfmp, tbrsnfmp and tbrpafmp are all bits 7, 6 and 5 of registers 008h, 00ch, 00eh and 03eh respectively. sta- tus bits tbtcksp, tbtsnsp and tbtpasp (bits 2 through 0) in register 00ah indicate a failure of aaclk (for p = 1 and 2) or baclk (for p = 3 and 4), aac1j1v1 (for p = 1 and 2) or bac1j1v1 (for p = 3 and 4) or aaspe (for p = 1 and 2) or baspe (for p = 3 and 4), if set to a 1, respectively. mask bits mtbtcfp, mtbtsfp and mtbtpfp, latched event bits tbtckep, tbtsnep and tbtpaep, performance values tbtckpmp, tbtsnpmp and tbtpapmp, and fault values tbtckfmp, tbtsnfmp and tbtpafmp are all bits 2 through 0 of registers 008h, 00ch, 00eh and 03eh respectively. status bit mcksp (bit 3) in register 00ah indicates a failure of srclk if set to a 1. mask bit mmckfp, latched event bit mckep, performance value mckpmp, and fault value mckfmp are all bit 3 of registers 008h, 00ch, 00eh and 03eh respectively. in addition, internal checks are made in the telecom bus interface block to determine if two or more channels of a t1mx28 device attempt to drive the same bus slot; if multiple channel drive attempts are detected within a group of seven channels an internal alarm event is indicated by status bit tbiesp (bit 1) in register 00bh being set to a 1. mask bit mtbiep, latched event bit tbieep, performance value tbiepmp, and fault value tbiefmp are all bit 1 of registers 009h, 00dh, 00fh and 03fh respectively. similarly, if two groups of seven channels on the same telecom bus attempt to drive this telecom bus simultaneously, an external alarm is declared by sta- tus bit tbxesp (bit 0) in register 00bh being set to a 1. for a single bus applications connect aaadd1 to bbuschk1 and bbuschk3 , aaadd2 to bbuschk2 and bbuschk4 , baadd1 to abuschk1 and abuschk3 , and baadd2 to abuschk2 and abuschk4 . to support an additional t1mx28 on a specific telecom bus connect aaadd1 of each device to abuschk1 and abuschk3 of the mate device, and aaadd2 of each device to abuschk2 and abuschk4 of the mate device. likewise for the b telecom bus. mask bit mtbxep, latched event bit tbxeep, performance value tbxepmp, and fault value tbxefmp are all bit 0 of registers 009h, 00dh, 00fh and 03fh respectively. parity errors are monitored on the drop telecom bus for all active slots from which signals are dropped. control bit tbpisp (bit 3) in register 007h includes adc1j1v1 (for p = 1 and 2) or bdc1j1v1 (for p = 3 and 4) and adspe (for p = 1 and 2) or bdspe (for p = 3 and 4) in the parity check if set to a 1. control bit tbpep (bit 2) in the same register selects even parity if set to a 1. status bit tbrpysp (bit 3) in register 00bh is set to a 1 whenever a parity error is detected. mask bit mtbrpyp, latched event bit tbrpyep, performance value tbrpypmp, and fault value tbrpyfmp are all bit 3 of registers 009h, 00dh, 00fh and 03fh respectively. bad parity may be forced onto the add telecom bus by setting control bit ftbtpep (bit 6) in register 01eh to a 1. - 79 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers device alarms can also be enabled to a separate alarm output lead aiao (for p = 1 and 2) or biao (for p = 3 and 4), which can be used as an interrupt or a board failure lead when wire "or ? ed" with the same or other t1mx28s. control bits etbrcfp, etbrsfp, etbrpfp (bits 7 through 5) in register 01bh, when set to a 1, enable the adclk (for p = 1 and 2) or bdclk (for p = 3 and 4), adc1j1v1 (for p = 1 and 2) or bdc1j1v1 (for p = 3 and 4) and adspe (for p = 1 and 2) or bdspe (for p = 3 and 4) failures to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) low. control bits etbtcfp, etbtsfp, etbtpfp (bits 2 through 0) in register 01bh, when set to a 1, enable the aaclk (for p = 1 and 2) or baclk (for p = 3 and 4), aac1j1v1 (for p = 1 and 2) or bac1j1v1 (for p = 3 and 4) and aaspe (for p = 1 and 2) or baspe (for p = 3 and 4) failures to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) low. likewise, emckfp (bit 3) in register 01bh, when set to a 1, enables the srclk failure to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) low. control bits etbrpyp, etbiep, etbxep (bits 3, 1 and 0) in register 01ch, when set to a 1, enable the parity error, internal telecom bus collision and external telecom bus collision to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) low. the alarm outputs aiao (for p = 1 and 2) or biao (for p = 3 and 4) are enabled by control bit enhwmp (bit 2) in register 006h being set to a 1. to provide for masking alarms on a particular assigned vt/tu, the adfail (for p = 1 and 2) or bdfail (for p = 3 and 4) input lead signals, which indicates a general signal failure, is sampled on the rising edge of adclk (for p = 1 and 2) or bdclk (for p = 3 and 4) and latched for the particular channel assigned to that vt/tu col- umn. if it is high, the data on add(0-7) (for p = 1 and 2) or bdd(0-7) (for p = 3 and 4) is invalid (e.g., sts-1 ais), and any alarms generated as a result will not interrupt the microprocessor. however, some consequent actions on the data should still be properly handled (e.g., generate ds1 ais); other actions (e.g., rdi) will not occur. adfail (for p = 1 and 2) or bdfail (for p = 3 and 4) is not included in bus parity. the following tables show the masking of lower order alarms by higher order alarms provided in the t1mx28 in both the mapping and demapping directions. t1mx28 demapper alarm masking the shaded area indicates which detectors are blocked for which condition. for example, vt ais blocks vt lop, vt unequipped, signal label mismatch, vt rdi, vt rfi and demap errors. condition reported signal fail vt ais detected vt lop detected vt unequipped detected signal label mismatch detected vt rdi detected vt rfi detected demap error signal failure x vt ais x vt lop x vt uneq. x sig label mismatch x vt rdi x vt rfi x demap error x - 80 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers t1mx28 demapper alarm masking figure 34 illustrates the operation of the shadow registers for a loss of signal (loss) alarm for any one of the twenty-eight mappers. the behavior shown in the diagram also applies to the other alarms in the same regis- ters (ais, lop, rdi, etc.) for per channel alarms. global control bit enpmfmp (bit 3) in register 006h is assumed to be set to a 1. global alarms (e.g. master clock fail - mcksp, mckep, etc.) are handled slightly differently in that the t1si pulse does not clear the event value as it does for per channel alarms. this figure assumes that control bits risep and fallp (bits 6 and 5) in the global configuration register 006h are set to 10 (latched event set on a positive transition only). please note that the los alarm causes a latched status indication lose (bit 5) in register x+14h, and that the latched bit is reset by the rising edge of the t1si pulse. the lospm status bit (bit 5) in register x+18h is a 1 whenever there is a transition to los during the last one- second interval or los is present at the end of the last one-second interval. the losfm status bit (bit 5) in register x+1ch is a 1 if the los alarm is active but did not become active during the previous one-second interval. figure 34. shadow register operation condition los ais oof yellow map error los x ds1 ais x oof x other t1si loss lose lospm losfm t=0 sec t=1 sec t=2 sec t=3 sec t=4 sec t=5 sec t=6 sec (bit 5 in x+1ch) (bit 5 in x+18h) (bit 5 in x+14h) (bit 5 in x+10h) note 1: for this example, latched events are set only on positive event transitions. note 2: lospm = loss + lose evaluated at one-second boundaries (where ? + ? is a logical or). note 3: losfm = loss & lose evaluated at one-second boundaries (where ? & ? is a logical and, and x is a logical inversion). - 81 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers serial port control interface the serial port control interface block is a serial interface that can be used to control and manage the external analog line transceivers operating in the ? host mode ? . this allows the system processor to have complete con- trol of the line transceivers through the t1mx28 microprocessor interface. the interface consists of data input leads (lsdip), data output leads (lsdop), and serial clock output leads (lsclkp) that are shared among all the transceivers. the source of lsclkp is the signal present on input leads alo (for p = 1 or 2) or blo (for p = 3 or 4). in addition, there is an individual chip select (lcsn ) for each transceiver, and an individual input (laisn) from each transceiver that may be used to generate a maskable interrupt; status bit xps (bit 7) in reg- ister x+10h indicates the signal on this lead. a mask xpm, a latched event value xpe, a pm value xppm and a fm value xpfm are available (bit 7) at register locations x+08h, x+14h, x+18h and x+1ch respectively. if desired, the signal at this lead may be used to indicate a loss of signal, which can be used to generate ais (see the line interface section for details). data to be written to the external transceiver is formatted as a two-byte message. the first byte is an address/ command byte and the second byte contains the data to be written or read. figure 35 illustrates the message and control formats associated with the transceiver serial i/o timing. the format of the address/command byte depends upon the external transceiver being controlled. please refer to the transceiver's data sheet for the command/data formats. the interface for controlling the external transceiver operates in the following way. the external transceiver selection (via lcsn ) is determined by the value written to three bits (bits 2, 1 and 0) in reg- ister 01ah. for example, a 000 value selects the transceiver for mapper 1. the microprocessor writes the com- mand byte to the line interface control register 017h. this is followed by writing the data byte to be written to the selected transceiver in line interface control register 018h. the serial message is sent on lsdop when a 1 is written to replace the 0 in the ensrpp bit (bit 4) in register 01ah. the ensrpp bit must be first written with a 0, followed by a 1, before another transfer can take place between the t1mx28 and the external trans- ceiver selected. broadcast capability to all transceivers is enabled when the control bit bdcstp (bit 7) in regis- ter 01ah is written with a 1. eight clock cycles later, the selected transceiver will respond by sending serial data on the lsdip input leads. the data is shifted in to the serial port data input register 019h, lsb first. figure 35. serial interface operation t1mx28 channel testing using the prbs generator and analyzer the prbs generator and analyzer block provides the ability to test each channel using the tributary and/or telecom bus loopback features provided. figure 36 below shows the general configuration used for testing any one of the twenty-eight channels. control bit tblpbkp (bit 7) in register 01eh, when set to a 1, loops back the telecom bus. setting tblpbkp to a 1 should only be done if all twenty-eight channels are off line, because normal operation for the channels not under test is suspended. for the telecom bus loopback to function, con- lcsn lsclkp lsdop lsdip addr d0 d1 d2 d3 d4 d5 d6 d7 r/w addr addr addr addr addr addr data input/output address/command byte d0 d1 d2 d3 d4 d5 d6 d7 - 82 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers trol bits in registers x+04h and x+05h also need to be set to enable the vt1.5/tu-11 to and from the same telecom bus slot. control bit dtlpbk (bit 7) in register x+0ch, when set to a 1, loops the encoder output clock, signaling, synchronization pulse and data back to the decoder input, providing a local loopback. it should be noted that if ais is to be sent to the line during a local loopback, it must be provided externally to the t1mx28 (e.g., via a t1fx8 or liu). it should also be noted that dtlpbk is only usable in asynchronous and modified byte-synchronous modes of operation; control bits mode1 and mode0 in register x+00h bits 1 and 9 must be set to 00, 01 or 11 only. the local loopback can be moved to the line interface transceiver or as a distant end remote loop back. if the distant end is a t1mx28, control bit dflpbk (bit 6) in register x+0ch may be set to a 1 to loop the received ds1 clock, signaling, synchronization and data to the transmit clock, signal- ing, synchronization and data. the prbs pattern may be inserted into any one or more mappers in place of the line decoder output by setting control bit sprbs (bit 4) in register x+0ch to a 1 when control bit eprbsap (bit 5) in global register 01ah is also set to a 1. the prbs analyzer is assigned to a mapper channel by the same control bits used to select an liu for the serial port, bits 2-0 in register 01ah. the analyzer monitors any one of the twenty-eight line decoder outputs. the output of the analyzer is readable by the microprocessor interface as status bit prbssp (bit 2) in register 00bh with a mask mprbsep, a latched value prbsep, a performance value prbspmp and a hard fault value prbsfmp, all bit 2 in registers 009h, 00dh, 00fh and 03fh respectively. the pattern is a 2 15 -1 bit pseudo-random binary sequence that follows the itu o.151 rec- ommendations, but is inverted. control bit txnrzpp (bit 0) in register 007h, when set to a 1, will make the internal prbs signal readable by standard test equipment connected to the ds1 line side of the t1mx28 map- per channel. the out of lock alarm can be made to go to external leads aiao (biao ), if desired, by setting control bit eprbsep, bit 2 in register 01ch, to a 1. figure 36. loopbacks and built-in prbs testing of the t1mx28 ds1 line line coder line decoder one of twenty-eight mapper channels dflpbk sprbs dtlpbk prbs gen. 1 0 1 1 0 0 demapper desynch. mapper synch. te l e c o m b u s i / f tblpbkp 0 1 prbs anal. te l e c o m b u s prbssp note: control and status bits are shown in bold font 1 0 sdaisl ais - 83 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers telecom bus interface the telecom bus interface contains the drivers and receivers for all the telecom bus signals. it multiplexes and demultiplexes all the data flowing from/to the telecom bus output and input control blocks. it also calculates the parity for aapar(bapar) and checks the parity against adpar(bdpar) for any driven slot used by this t1mx28 (both odd and even parity are selectable, and aapar(bapar) may be calculated on aad(0-7) (bad(0-7)) only or on the combination of aad(0-7)(bad(0-7)), aaspe(baspe) and aac1j1v1 (bac1j1v1)); slots that are not selected are skipped. telecom bus assignments can be used to localize parity errors. this block generates the aaadd(1-2) (baadd(1-2) ) signals for any active slot driven by this t1mx28, to permit using external buffers. aaadd(1-2) (baadd(1-2) ) are generally not required as the t1mx28 outputs are tristated; however, if an application requires bus drivers with different characteristics or with additional drive this signal is available. spe is valid during the sts-1 or sts-3 synchronous payload. c1j1v1 defines the starting position of the vt/tus on the bus. note that aad(0-7)(bad(0-7)) data is pre-fetched to be ready to be clocked into an external device on the rising edge of aaclk(baclk); if the column or byte is a stuff position in the sts-1 the data remains present until the slot is a valid spe (aaspe(baspe) active). for systems that use the telecom bus to multiplex in transport or path overhead information (e.g., h4 via the transwitch phast-1), the adaten(bdaten) leads should be tied externally to aaspe(baspe) so that spe inactive bytes are not driven during the rising edge of aaclk(baclk). when the aad(0-7)(bad(0-7)) signals are delayed one aaclk(baclk) clock period by control bit tbddp (bit 3) in register 01eh, the aaspe(baspe) signal into the adaten(bdaten) must be delayed by one aaclk(baclk) clock period to align with the data output to the add bus. if required, the mastera and masterb input leads may be grounded so that the sts-1 poh and stuff columns or bytes may be driven with idle (all-zeros with valid parity) or an assigned vt value such that bus parity errors are prevented. the following table shows which bytes are driven on the telecom bus in vari- ous modes; note that each sts-1 or tug-3 is treated separately. under microprocessor interface control the data, aad(0-7)(bad(0-7)), may be delayed one clock period by control bit tbddp (bit 3) in register 01eh, and the active clock edges of adclk(bdclk) and the active clock edges of adclk(bdclk) and aaclk(baclk) may be inverted by control bits tbrcip (bit 4) and tbtcip (bit 5) in the same register being set to a 1. - 84 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers the telecom bus interface also provides a loopback mode for device testing. internally, the entire telecom bus is looped. individual channels are tested by enabling them through the serial port select byte for the prbs analyzer and the per channel select bit for the prbs generator, as described above. the mapper timing block supplies overall mapper timing to both the synchronizer/mapper and the desynchro- nizer/demapper blocks based on the telecom bus clocks, c1j1v1 and spe signals received. sonet and sdh have different stuff column positions. in sonet format v1 is coincident with v1 #1; in sdh format for tug-3, v1 starts six tug-3 clock pulses early. a bit in the common control register is used to select this. the external clock, alo(blo), are independent 1.544 mhz clocks for the purpose of generating a system-synchro- nized clock for clocking in data and signaling for byte-synchronous operation. the t1mx28 can operate at 6.48 mhz or 19.44 mhz, as shown in figures 37 and 38. the bus speed is deter- mined by the configi lead; if tied low, the t1mx28 operates in 19.44 mhz mode with 84 vt1.5/tu-11 slots; if tied high, the t1mx28 operates in 6.48 mhz mode with 28 vt1.5/tu-11 slots. for gapped clock situations an allowance for up to 10% higher speed needs to be made. the t1mx28 cannot account for extra columns, so spe being inactive for extra columns must be used. for 19.44 mhz operation in sonet or sdh au-3 mapping, the three j1 signals can be anywhere in the sts- 1 or au-3 for both adc1j1v1(bdc1j1v1) and aac1j1v1(bac1j1v1); hence separate tracking is provided for each. control bit vc3vc4p (bit 1) in register 007h must be set to a 1. in this mode of operation there are no restrictions on the three j1 positions in aac1j1v1(bac1j1v1) for asynchronous or modified byte-synchro- nous applications. however, if byte-synchronous modes are used, the three j1s in aac1j1v1(bac1j1v1) cannot move with respect to each other, since alo(blo) must be locked to aaclk(baclk) and aac1j1v1 (bac1j1v1). if all channels are mapped to a specific sts-1, the restriction does not apply as long as the j1 reference for alo(blo) is the same sts-1. adaten(bdaten) and mastera (masterb ) leads assigned vt unassigned vt poh and stuff toh toh condition followed by assigned vt followed by poh or stuff adaten(bdaten) high; mastera (masterb ) high driven aaadd(1-2) (baadd(1-2) ) low float aaadd(1-2) (baadd(1-2) ) high float aaadd(1-2) (baadd(1-2) ) high driven to vt value that follows aaadd(1-2) (baadd(1-2) ) low float aaadd(1-2) (baadd(1-2) ) high adaten(bdaten) high; mastera (masterb ) low driven aaadd(1-2) (baadd(1-2) ) low float aaadd(1-2) (baadd(1-2) ) high driven to zero aaadd(1-2) (baadd(1-2) ) high driven to vt value that follows aaadd(1-2) (baadd(1-2) ) low driven to zero aaadd(1-2) (baadd(1-2) ) high adaten(bdaten) = aaspe(baspe); mastera (masterb ) high (see note) driven aaadd(1-2) (baadd(1-2) ) low float aaadd(1-2) (baadd(1-2) ) high float aaadd(1-2) (baadd(1-2) ) high float aaadd(1-2) (baadd(1-2) ) high float aaadd(1-2) (baadd(1-2) ) high adaten(bdaten) = aaspe(baspe); mastera (masterb ) low (see note) driven aaadd(1-2) (baadd(1-2) ) low float aaadd(1-2) (baadd(1-2) ) high driven to zero aaadd(1-2) (baadd(1-2) ) high float aaadd(1-2) (baadd(1-2) ) high float aaadd(1-2) (baadd(1-2) ) high adaten(bdaten) low float aaadd(1-2) (baadd(1-2) ) high float aaadd(1-2) (baadd(1-2) ) high float aaadd(1-2) (baadd(1-2) ) high float aaadd(1-2) (baadd(1-2) ) high float aaadd(1-2) (baadd(1-2) ) high note: the aaspe(baspe) signal into the adaten(bdaten) input must be delayed by one aaclk(baclk) clock period when the telecom bus data delay tbddp (bit 3 in register 01eh) is enabled. - 85 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers figure 37. telecom bus structure; sonet or vc-3 sdh; telecom bus @ 6.48 mhz c1 c1 c1 c1 h1h2h3 v1. . . . . . . . . . .v1 v2. . . . . . . . . . .v2 v3. . . . . . . . . . .v3 v4. . . . . . . . . . .v4 v5 v5 i v5 v1v1v1. . . . . . . . . . . . .v1v1 j1 v2v2v2. . . . . . . . . . . . .v2v2 j1 v3v3. . . . . . . . . . . . .v3v3 j1 v4v4v4. . . . . . . . . . . . .v4v4 j1 z6 j2 v5 v5 z7 b3 c2 g1 f2 h4 z4 z5 z3 d j 1 v 1 # 1 spe c1j1v1 clk c 1 1 36 1 90 - 86 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers the signals shown in figure 37 are valid for the entire sts-1 signal, representing an overlay of all 36 rows of 90 bytes each. each of the 28 vt1.5s occupy 3 columns (counted from the sts-1 path overhead and with the two stuff columns the same) with transport overhead (toh) taking 3 columns (shaded), the sts-1 path over- head taking a column (j1, b3.z5) and 2 columns of fixed stuff (crosshatched). spe is only low during toh. c1j1v1 is high during the 4 c1 bytes shown, the 4 j1 bytes shown and the one v1 #1 byte shown. for vt#1 of vtg#1, j2, z6 and z7 are also shown. figure 39 below provides the column assignments for an sts-1 sys- tem bus. the sts-3 case is as depicted in figure 38, with the columns of the three sts-1s byte-interleaved; in this case, the three c1 bytes occur together, but the individual j1 bytes can occur in any of the 87 columns of the sts-1 or vc-3. fixed offset places v5s after v1s. figure 40 below provides the column assignments for the sts-3. figure 38. telecom bus structure; tug-3 sdh; telecom bus @ 19.44 mhz figure 38 above shows the sdh format for three tug-3s in a vc-4. control bit vc3vc4p (bit 1) in register 007h must be set to a 0. figure 41 below provides the column assignments for an stm-1. each tug-3 con- tains seven tug-2s and each tug-2 contains four tu-11s. the signals shown are an overlay of all 36 rows of 270 bytes each. spe is low only for the stm-1 transport overhead (toh), which is the first 9 columns (shaded). c1j1v1 is high for the first c1 byte of the toh, the j1 byte of the vc-4 path overhead (poh) and the first column of each tug-3 (null pointer indications). fixed offset for v5 generation of 78 places system-bound v5 bytes after v1 bytes for asynchronous mode only. in the byte-synchronous mode (modified byte-synchro- nous or true byte-synchronous operation), the initial location of the v5 bytes is defined by the phase between the add bus reference, aac1j1v1 or bac1v1j1, and rsyncn. if the relationship changes slowly, v1 and v2 are incremented or decremented to track the signal. abrupt changes in rsyncn will cause a new value of v1 and v2 to be generated with a corresponding ndf indication in v1. c1c1c1 j1 b3 c2 g1 f2 h4 z3 z4 z5 n p i n p i n p i v1v1v1. . . . . . . . . . . .v1 v5 v5 #1 #2 #3. . . . . . . . . . . . #3 # # # 1 2 3 # # # 1 2 3 c1c1c1 1 270 v2v2v2. . . . . . . . . . . .v2 #1 #2 #3. . . . . . . . . . . . #3 v5 v5 v5 spe j 1 v c1j1v1 c 1 36 1 1 - 87 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers multiplex format and mapping information sts-1 vt1.5 (1.544 mbit/s) multiplex format the following diagram and table illustrate the mapping of the 28 vt1.5s into a sts-1 spe. column 1 is assigned to carry the path overhead bytes. figure 39. sts-1 spe mapping 1 2 3 27 123 4 27 vt vt vt vt vt 3 columns 1315987 1.5 # 28 1.5 #2 1.5 # 28 1.5 #1 1.5 # 28 vt vt vt vt 1.5 #1 1.5 #2 1.5 #1 1.5 #2 30 29 58 60 vt1.5 r r r r r r r r r j1 b3 c2 g1 f2 h4 z3 z4 z5 sts-1 spe r r r r r r r r r - 88 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers sts-1 mapping vt# registers x+04h for drop and x+05h for add vt1.5 column numbers* 76543210 0xxxxxxx no vt selected 1 10000000 2, 31, 60 2 10000100 3, 32, 61 3 10001000 4, 33, 62 4 10001100 5, 34, 63 5 10010000 6, 35, 64 6 10010100 7, 36, 65 7 10011000 8, 37, 66 8 10000001 9, 38, 67 9 10000101 10, 39, 68 10 10001001 11, 40, 69 11 10001101 12, 41, 70 12 10010001 13, 42, 71 13 10010101 14, 43, 72 14 10011001 15, 44, 73 15 10000010 16, 45, 74 16 10000110 17, 46, 75 17 10001010 18, 47, 76 18 10001110 19, 48, 77 19 10010010 20, 49, 78 20 10010110 21, 50, 79 21 10011010 22, 51, 80 22 10000011 23, 52, 81 23 10000111 24, 53, 82 24 10001011 25, 54, 83 25 10001111 26, 55, 84 26 10010011 27, 56, 85 27 10010111 28, 57, 86 28 10011011 29, 58, 87 * note: columns 30 and 59 carry fixed stuff bytes. column 1 is assigned for the poh bytes. - 89 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers sts-3/au-3 vt1.5/tu-11 (1.544 mbit/s) multiplex format mapping the following diagram and table illustrate the mapping of the vt1.5/tu-11s into a sts-3/au-3 spe. each sts-3 carries three sts-1s. column 1 in each sts-1/au-3 is assigned to carry the path overhead bytes. figure 40. sts-3/au-3 mapping sts-1 #1 #2 #3 sts-3/au-3 spe 1 2 3 27 12 3 4 27 vt vt vt vt vt vt 1 261 3 columns 13159 871 87 j1 b3 c2 g1 f2 h4 z3 z4 z5 j1 b3 c2 g1 f2 h4 z3 z4 z5 j1 b3 c2 g1 f2 h4 z3 z4 z5 1.5 # 28 1.5 #2 1.5 # 28 1.5 # 28 vt vt vt vt vt vt vt 1.5 #1 1.5 #2 1.5 #1 1.5 #2 1.5 #1 1.5 #2 1.5 # 28 1.5 #1 1.5 #2 30 29 58 60 1 vt1.5 3 r r r r r r r r r r r r r r r r r r 2 vt 1.5 #1 87 vt 1.5 # 28 - 90 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers sts-3 au-3 mapping * note: columns 88, 89, 90, 175, 176, 177 are fixed stuff. vt tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vt/tu column numbers vt tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vt/tu column numbers vt tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vt/tu column numbers* tbtval or tbrval = 0 no tu selected 1 0 0 0 0 0 0 0 4 91 178 29 0 1 0 0 0 0 0 5 92 179 57 1 0 0 0 0 0 0 6 93 180 2 0 0 0 0 1 0 0 7 94 181 30 0 1 0 0 1 0 0 8 95 182 58 1 0 0 0 1 0 0 9 96 183 3 0 0 0 1 0 0 0 10 97 184 31 0 1 0 1 0 0 0 11 98 185 59 1 0 0 1 0 0 0 12 99 186 4 0 0 0 1 1 0 0 13 100 187 32 0 1 0 1 1 0 0 14 101 188 60 1 0 0 1 1 0 0 15 102 189 5 0 0 1 0 0 0 0 16 103 190 33 0 1 1 0 0 0 0 17 104 191 61 1 0 1 0 0 0 0 18 105 192 6 0 0 1 0 1 0 0 19 106 193 34 0 1 1 0 1 0 0 20 107 194 62 1 0 1 0 1 0 0 21 108 195 7 0 0 1 1 0 0 0 22 109 196 35 0 1 1 1 0 0 0 23 110 197 63 1 0 1 1 0 0 0 24 111 198 8 0 0 0 0 0 0 1 25 112 199 36 0 1 0 0 0 0 1 26 113 200 64 1 0 0 0 0 0 1 27 114 201 9 0 0 0 0 1 0 1 28 115 202 37 0 1 0 0 1 0 1 29 116 203 65 1 0 0 0 1 0 1 30 117 204 10 0 0 0 1 0 0 1 31 118 205 38 0 1 0 1 0 0 1 32 119 206 66 1 0 0 1 0 0 1 33 120 207 11 0 0 0 1 1 0 1 34 121 208 39 0 1 0 1 1 0 1 35 122 209 67 1 0 0 1 1 0 1 36 123 210 12 0 0 1 0 0 0 1 37 124 211 40 0 1 1 0 0 0 1 38 125 212 68 1 0 1 0 0 0 1 39 126 213 13 0 0 1 0 1 0 1 40 127 214 41 0 1 1 0 1 0 1 41 128 215 69 1 0 1 0 1 0 1 42 129 216 14 0 0 1 1 0 0 1 43 130 217 42 0 1 1 1 0 0 1 44 131 218 70 1 0 1 1 0 0 1 45 132 219 15 0 0 0 0 0 1 0 46 133 220 43 0 1 0 0 0 1 0 47 134 221 71 1 0 0 0 0 1 0 48 135 222 16 0 0 0 0 1 1 0 49 136 223 44 0 1 0 0 1 1 0 50 137 224 72 1 0 0 0 1 1 0 51 138 225 17 0 0 0 1 0 1 0 52 139 226 45 0 1 0 1 0 1 0 53 140 227 73 1 0 0 1 0 1 0 54 141 228 18 0 0 0 1 1 1 0 55 142 229 46 0 1 0 1 1 1 0 56 143 230 74 1 0 0 1 1 1 0 57 144 231 19 0 0 1 0 0 1 0 58 145 232 47 0 1 1 0 0 1 0 59 146 233 75 1 0 1 0 0 1 0 60 147 234 20 0 0 1 0 1 1 0 61 148 235 48 0 1 1 0 1 1 0 62 149 236 76 1 0 1 0 1 1 0 63 150 237 21 0 0 1 1 0 1 0 64 151 238 49 0 1 1 1 0 1 0 65 152 239 77 1 0 1 1 0 1 0 66 153 240 22 0 0 0 0 0 1 1 67 154 241 50 0 1 0 0 0 1 1 68 155 242 78 1 0 0 0 0 1 1 69 156 243 23 0 0 0 0 1 1 1 70 157 244 51 0 1 0 0 1 1 1 71 158 245 79 1 0 0 0 1 1 1 72 159 246 24 0 0 0 1 0 1 1 73 160 247 52 0 1 0 1 0 1 1 74 161 248 80 1 0 0 1 0 1 1 75 162 249 25 0 0 0 1 1 1 1 76 163 250 53 0 1 0 1 1 1 1 77 164 251 81 1 0 0 1 1 1 1 78 165 252 26 0 0 1 0 0 1 1 79 166 253 54 0 1 1 0 0 1 1 80 167 254 82 1 0 1 0 0 1 1 81 168 255 27 0 0 1 0 1 1 1 82 169 256 55 0 1 1 0 1 1 1 83 170 257 83 1 0 1 0 1 1 1 84 171 258 28 0 0 1 1 0 1 1 85 172 259 56 0 1 1 1 0 1 1 86 173 260 84 1 0 1 1 0 1 1 87 174 261 sts-1 #1, au-3 a sts-1 #2, au-3 b sts-1 #3, au-3 c - 91 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers tu-11 - vc-4 multiplex format mapping the following figure 41 and table illustrate the mapping of tu-11s into a vc-4. figure 41. stm-1/vc-4 mapping 1 2 3 27 123 4 27 2 3 4 2 3 4 2 3 4 67 2 712 7 n p i n p i 7 n p i 1 p o h 1 261 3 columns tu-11 tug-2 tug-3 13159 86186 vc-4 86 1 11 11 3 7 1 1 10 4 - 92 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers tu-11 - vc-4 multiplex format mapping tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vc-4 column numbers tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vc-4 column numbers tu # registers x+04h or x+05h 6 5 4 3 2 1 0 vc-4 column numbers tbtval or tbrval = 0 no tu selected 1 0 0 0 0 0 0 0 10 94 178 29 0 1 0 0 0 0 0 11 95 179 57 1 0 0 0 0 0 0 12 96 180 2 0 0 0 0 1 0 0 13 97 181 30 0 1 0 0 1 0 0 14 98 182 58 1 0 0 0 1 0 0 15 99 183 3 0 0 0 1 0 0 0 16 100 184 31 0 1 0 1 0 0 0 17 101 185 59 1 0 0 1 0 0 0 18 102 186 4 0 0 0 1 1 0 0 19 103 187 32 0 1 0 1 1 0 0 20 104 188 60 1 0 0 1 1 0 0 21 105 189 5 0 0 1 0 0 0 0 22 106 190 33 0 1 1 0 0 0 0 23 107 191 61 1 0 1 0 0 0 0 24 108 192 6 0 0 1 0 1 0 0 25 109 193 34 0 1 1 0 1 0 0 26 110 194 62 1 0 1 0 1 0 0 27 111 195 7 0 0 1 1 0 0 0 28 112 196 35 0 1 1 1 0 0 0 29 113 197 63 1 0 1 1 0 0 0 30 114 198 8 0 0 0 0 0 0 1 31 115 199 36 0 1 0 0 0 0 1 32 116 200 64 1 0 0 0 0 0 1 33 117 201 9 0 0 0 0 1 0 1 34 118 202 37 0 1 0 0 1 0 1 35 119 203 65 1 0 0 0 1 0 1 36 120 204 10 0 0 0 1 0 0 1 37 121 205 38 0 1 0 1 0 0 1 38 122 206 66 1 0 0 1 0 0 1 39 123 207 11 0 0 0 1 1 0 1 40 124 208 39 0 1 0 1 1 0 1 41 125 209 67 1 0 0 1 1 0 1 42 126 210 12 0 0 1 0 0 0 1 43 127 211 40 0 1 1 0 0 0 1 44 128 212 68 1 0 1 0 0 0 1 45 129 213 13 0 0 1 0 1 0 1 46 130 214 41 0 1 1 0 1 0 1 47 131 215 69 1 0 1 0 1 0 1 48 132 216 14 0 0 1 1 0 0 1 49 133 217 42 0 1 1 1 0 0 1 50 134 218 70 1 0 1 1 0 0 1 51 135 219 15 0 0 0 0 0 1 0 52 136 220 43 0 1 0 0 0 1 0 53 137 221 71 1 0 0 0 0 1 0 54 138 222 16 0 0 0 0 1 1 0 55 139 223 44 0 1 0 0 1 1 0 56 140 224 72 1 0 0 0 1 1 0 57 141 225 17 0 0 0 1 0 1 0 58 142 226 45 0 1 0 1 0 1 0 59 143 227 73 1 0 0 1 0 1 0 60 144 228 18 0 0 0 1 1 1 0 61 145 229 46 0 1 0 1 1 1 0 62 146 230 74 1 0 0 1 1 1 0 63 147 231 19 0 0 1 0 0 1 0 64 148 232 47 0 1 1 0 0 1 0 65 149 233 75 1 0 1 0 0 1 0 66 150 234 20 0 0 1 0 1 1 0 67 151 235 48 0 1 1 0 1 1 0 68 152 236 76 1 0 1 0 1 1 0 69 153 237 21 0 0 1 1 0 1 0 70 154 238 49 0 1 1 1 0 1 0 71 155 239 77 1 0 1 1 0 1 0 72 156 240 22 0 0 0 0 0 1 1 73 157 241 50 0 1 0 0 0 1 1 74 158 242 78 1 0 0 0 0 1 1 75 159 243 23 0 0 0 0 1 1 1 76 160 244 51 0 1 0 0 1 1 1 77 161 245 79 1 0 0 0 1 1 1 78 162 246 24 0 0 0 1 0 1 1 79 163 247 52 0 1 0 1 0 1 1 80 164 248 80 1 0 0 1 0 1 1 81 165 249 25 0 0 0 1 1 1 1 82 166 250 53 0 1 0 1 1 1 1 83 167 251 81 1 0 0 1 1 1 1 84 168 252 26 0 0 1 0 0 1 1 85 169 253 54 0 1 1 0 0 1 1 86 170 254 82 1 0 1 0 0 1 1 87 171 255 27 0 0 1 0 1 1 1 89 172 256 55 0 1 1 0 1 1 1 89 173 257 83 1 0 1 0 1 1 1 90 174 258 28 0 0 1 1 0 1 1 91 175 259 56 0 1 1 1 0 1 1 92 176 260 84 1 0 1 1 0 1 1 93 177 261 tug-3 a tug-3 b tug-3 c - 93 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers internal ring port the internal ring port is used in ushr/p ring applications to communicate rei (febe) and rdi information between two mated groups of seven mappers (mappers no. 1 and no. 15, no. 2 and no. 16 through no. 14 and no. 28 are interconnected). the internal ring port consists of twenty-four internal connections, twelve internal outputs and twelve internal inputs. the internal output port connections for each mated group of seven mappers are output port clock (orpckop), output port frame (orpfmop), output port data (orpdtop) and the input port connections for each mated group of seven mappers are input port clock (irpckip), input port frame (irpfmip), input port data (irpdtip). figure 42 shows the ring port operation. the information consists of twenty-eight eight-bit fields, one for each channel. the first four bits are rei-v (febe), rdi-vpd, rdi-vsd, and rdi-vcd. the last four bits are not used. the information is accumulated for all twenty-eight channels and sent as a burst of 56 bits or 4 orpdtop. the orpckop is a ? divide by ten ? derivative of adclk(bdclk). internal ring operation is enabled with the control bit ringen (bit 4) in register x+0bh. when set to zero, normal operations are performed. when set to one, ring mode is enabled. the information incoming on irpdti is stored in register x+3ah, bits 3-0 for access by the microprocessor. the designation for these bits is rgfebe-v (bit 3), rgrdi-vpd (bit 2), rgrdi-vsd (bit 1), and rgrdi-vcd (bit 0). the four remaining bits will be designated ? unused ? . figure 42. internal ring port operation typically for ring operation, the operating drop side demapper returns rei-v, rdi-vpd, rdi-vsd and rdi- vcd to its own add bus (control bit ringen (bit 4) in register x+0bh is set to 0). the rei and rdi information is also available on the ring port. hence, the standby demapper, through monitoring the drop side for alarms does not add rei or rdi data into the add direction overhead from the drop alarm. instead, it sets ringen=1 and takes the rei and rdi information from the operating drop side mapper. channel 1 0 1 2 3 4 5 6 7 0 7 channel 7 0 1 2 3 4 5 6 7 0 1 rei-v rdi- rdi- rdi- vcd vsd vpd orpckop irpckiq orpdtop irpdtiq orpfmop irpfmiq ring port internal connections note: p=1-4, q=1-4 orpckop to irpckiq p=1, q=3 p=2, q=4 p=3, q=1 p=4, q=2 orpfmop to irpfmiq p=1, q=3 p=2, q=4 p=3, q=1 p=4, q=2 orpdtop to irpdtiq p=1, q=3 p=2, q=4 p=3, q=1 p=4, q=2 - 94 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers test access port introduction the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides observability and controllability for the interface leads of the device. the test access port block, which imple- ments the boundary scan functions, consists of a test access port (tap) controller, instruction and test data registers, and a boundary scan register path bordering the input and output leads, as illustrated in figure 43. the boundary scan test bus interface consists of four input signals (i.e., the test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs ) input signals) and a test data output (tdo) output signal. a brief description of boundary scan operation is provided below; further information is available in the ieee standard document. the tap controller receives external control information via a test clock (tck) signal, a test mode select (tms) signal, and a test reset (trs ) signal, and it sends control signals to the internal scan paths. the scan path architecture consists of a three-bit serial instruction register and two or more serial test data registers. the instruction and data registers are connected in parallel between the serial test data input (tdi) and test data output (tdo) signals. the test data input (tdi) signal is routed to both the instruction and test data reg- isters and is used to transfer serial data into a register during a scan operation. the test data output (tdo) is selected to send data from either register during a scan operation. when boundary scan testing is not being performed, the boundary scan register is transparent, allowing the input and output signals at the device leads to pass to and from the t1mx28 device ? s internal logic, as illus- trated in figure 43. during boundary scan testing, the boundary scan register disables the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. a timing diagram for the boundary scan feature is provided in figure 18. boundary scan support the maximum frequency the t1mx28 device will support for boundary scan is 10 mhz. the t1mx28 device performs the following boundary scan test instructions: - extest (000) - sample/preload (010) - bypass (111) it should be noted that the capture - ir state (instruction_capture attribute of bsdl) is 011. extest test instruction: one of the required boundary scan tests is the external boundary test (extest) instruction. when this instruction is shifted in, the t1mx28 device is forced into an off-line test mode. while in this test mode, the test bus can shift data through the boundary scan registers to control the external t1mx28 input and output leads. sample/preload test instruction: when the sample/preload instruction is shifted in, the t1mx28 device remains fully operational. while in this test mode, t1mx28 input data, and data destined for device outputs, can be captured and shifted out for inspection. the data is captured in response to control signals sent to the tap controller. bypass test instruction: when the bypass instruction is shifted in, the t1mx28 device remains fully operational. while in this test mode, a scan operation will transfer serial data from the tdi input, through an internal scan cell, to the tdo lead. the purpose of this instruction is to abbreviate the scan path through the circuits that are not being tested. it should be noted that the bypass test instruction will have a four clock delay between tdi and tdo due to the fact that the t1mx28 consists of four identical ds1mx7 mapper cores (see figure 43). - 95 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers boundary scan reset specific control of the trs lead is required in order to ensure that the boundary scan logic does not interfere with normal device operation. this lead must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the test access port (tap) controller during power-up of the t1mx28. if boundary scan testing is to be performed and the lead is held low, then a pull-down resistor value should be chosen which will allow the tester to drive this lead high, but still meet the v il requirements listed in the ? input, output and input/output parameters ? section of this data sheet for worst case leakage currents of all devices sharing this pull-down resistor. figure 43. boundary scan schematic tap controller bypass register instruction register boundary scan serial test data core logic signal input and output leads (solder balls on bottom surface of pbga package) tap controller bypass register instruction register core logic tap controller bypass register instruction register tdi in core logic tap controller bypass register instruction register tdo out core logic 1 23 4 3 boundary scan register controls tck tms trs note: lead locations are shown for illustration only, and do not correspond to the physical device leads. - 96 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers boundary scan chain the t1mx28 contains four identical ds1mx7 vlsi chips, each of which has its own boundary scan chain. since these chips drive common input and output leads, it is not feasible to develop a bsdl file for the overall device. instead, to facilitate customer testing of the t1mx28, transwitch has developed a module-level test approach that utilizes a device netlist 1 (prepared in a teradyne tester format) and a specially modified bsdl 2 file for the t1mx28. the associated files and explanatory material are combined in a .zip file format. this file, together with other t1mx28 product documentation, is available on the transwitch internet web site (www.transwitch.com). it can be located by using the ? product finder ? segment on the home page to select product name t1mx28, or by entering t1mx28 in the search box and selecting the first response. device reset procedure after power-up the t1mx28 requires a hardware reset. this reset will reset all the per channel registers in the memory map. it will also reset all of the global registers at addresses 04h through 03fh. a low placed on the rsti lead for at least 10 cycles of pcki after all clocks become stable will accomplish the hardware reset. a global software reset is also available and should be applied at least 10 ms after power-up. this resets the internal state machines. it does not change the state of any of the control registers, performance counters and latched shadow registers. writing a 91h to control byte resetp (p = 1- 4) in register 005h places the group number p (7 channels) of the t1mx28 in a reset state. writing a value other than 91h to control byte resetp will take the group of 7 channels of the t1mx28 out of the reset state. the resetp register can be read to determine the reset state of the t1mx28. a value of 01h in the resetp register indicates the group of 7 chan- nels of the t1mx28 is in a reset state; a value of 00h indicates the t1mx28 is not in reset. a per channel ver- sion of this function is available by writing a 1 to control bit rstch (bit 5) in register x0ch followed by writing a 0 to control bit rstch. changing the mode of operation of a mapper should be followed by a per channel software reset (rstch). the mode bits can be found in mapper per channel registers x+00h through x+02h (explos, datacom, enzc, lcode, encod, mode1, mode0 and crc6). not resetting the mapper after changing other mode control bits will have minimal effect. if all 28 channels of the t1mx28 are not implemented in an application, the channels that are not used should be powered down (control bit idle, bit 7 in register x+00h is set to a 0) and all interrupts masked (registers x+09h through x+0bh set to ffh). 1. the net list is a text file that describes the interconnections of the four chips within the device and their connections to the t1mx28 package leads. 2. the boundary scan description language (bsdl) file describes the boundary scan chain for each silicon chip of the t1mx28 device. this must be used four times to provide complete coverage of all boundary scan cells in the t1mx28. - 97 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers memory map the t1mx28 memory map is organized into 32 blocks which are selectable both by address leads addr(8-0) and select lines selip . there are 4 common groups that provide control and status bits common to groups of 7 mapper channels each and 28 individual channel groups that provide the control and status bits for each mapper channel. group selection hex address range: addr(8-0) channel functions seli 1 seli 2 seli3 seli 4 0111 000 - 03f common group for #1 through #7 component id. serial port control, global control, device controls and interrupt control 0111 040 - 07f #1status, control, pm/fm and error counters 0111 080 - 0bf #2status, control, pm/fm and error counters 0111 0c0 - 0ff #3status, control, pm/fm and error counters 0111 100 - 13f #4status, control, pm/fm and error counters 0111 140 - 17f #5status, control, pm/fm and error counters 0111 180 - 1bf #6status, control, pm/fm and error counters 0111 1c0 - 1ff #7status, control, pm/fm and error counters 1011 000 - 03f common group for #8 through #14 component id. serial port control, global control, device controls and interrupt control 1011 040 - 07f #8status, control, pm/fm and error counters 1011 080 - 0bf #9status, control, pm/fm and error counters 1011 0c0 - 0ff #10status, control, pm/fm and error counters 1011 100 - 13f #11status, control, pm/fm and error counters 1011 140 - 17f #12status, control, pm/fm and error counters 1011 180 - 1bf #13status, control, pm/fm and error counters 1011 1c0 - 1ff #14status, control, pm/fm and error counters 1101 000 - 03f common group for #15 through #21 component id. serial port control, global control, device controls and interrupt control 1101 040 - 07f #15status, control, pm/fm and error counters 1101 080 - 0bf #16status, control, pm/fm and error counters 1101 0c0 - 0ff #17status, control, pm/fm and error counters 1101 100 - 13f #18status, control, pm/fm and error counters 1101 140 - 17f #19status, control, pm/fm and error counters 1101 180 - 1bf #20status, control, pm/fm and error counters 1101 1c0 - 1ff #21status, control, pm/fm and error counters - 98 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers common memory map notes: *r/w: read/write; r: read-only; w: write-only; r/w=clr: read/write zero bits only (one bits ignored during write). bits shown as 'r' and bytes shown as 'reserved' must be set to 0/00h for proper device operation, where write capability is provided. spare registers must not be accessed by the microprocessor. four groups of common memory blocks are provided, as described above, each controlling a group of 7 chan- nels. (p = 1 - 4) 1110 000 - 03f common group for #22 through #28 component id. serial port control, global control, device controls and interrupt control 1110 040 - 07f #22status, control, pm/fm and error counters 1110 080 - 0bf #23status, control, pm/fm and error counters 1110 0c0 - 0ff #24status, control, pm/fm and error counters 1110 100 - 13f #25status, control, pm/fm and error counters 1110 140 - 17f #26status, control, pm/fm and error counters 1110 180 - 1bf #27status, control, pm/fm and error counters 1110 1c0 - 1ff #28status, control, pm/fm and error counters address (hex) mode* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000 r mi7p=1 mi6p=1 mi5p=0 mi4p=1 mi3p=0 mi2p=1 mi1p=1 mi0p=1 001 r pn3p=1 pn2p=0 pn1p=0 pn0p=1 mi11p=0 mi10p=0 mi9p=0 mi8p=0 002 r pn11p=0 pn10p=0 pn9p=0 pn8p=0 pn7p=0 pn6p=1 pn5p=1 pn4p=0 003 r v3p=0 v2p=0 v1p=1 v0p=0 pn15p=0 pn14p=0 pn13p=0 pn12p=1 004 r/w notebook(p) 005 r/w resetp 006 r/w simp risep fallp ipolp enpmfmp enhwmp r r 007 r/w tcaep rcaep sdhp rxnrzpp tbpisp tbpep vc3vc4p txnrzpp 008 r/w mtbrcfp mtbrsfp mtbrpfp r mmckfp mtbtcfp mtbtsfp mtbtpfp 009 r/w r r r r mtbrpyp mprbsep mtbiep mtbxep 00a r tbrcksp tbrsnsp tbrpasp r mcksp tbtcksp tbtsnsp tbtpasp 00b r r r r r tbrpysp prbssp tbiesp tbxesp 00c r/w=clr tbrckep tbrsnep tbrpaep r mckep tbtckep tbtsnep tbtpaep 00d r/w=clr r r r r tbrpyep prbsep tbieep tbxeep 00e r/w=clr tbrckpmp tbrsnpmp tbrpapmp r mckpmp tbtckpmp tbtsnpmp tbtpapmp 00f r/w=clr r r r r tbrpypmp prbspmp tbiepmp tbxepmp group selection hex address range: addr(8-0) channel functions seli 1 seli 2 seli3 seli 4 - 99 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers per channel memory map note: in the address, x= 040h for ds1 channel #1; 080h for ds1 channel #2; 0c0h for ds1 channel #3; 100h for ds1 channel #4; 140h for ds1 channel #5; 180h for ds1 channel #6; 1c0h for ds1 channel #7 of a group. the group is selected by leads selip , where p selects the group of channels (p=1 selects channels 1-7, p=2 selects channels 8-14, p=3 selects channels 15-21 and p=4 selects channels 22-28). 010 - spare 011 r r ch7p ch6p ch5p ch4p ch3p ch2p ch1p 012 - spare 013 r gxpep gdmpep glosep gmpep gdaisep grpoep gpgoep gcvoep 014 r gfeoep gbipoep gvaisep glopep grfiep guneep gslmep grdiep 015 r/w gxpmp gdmpmp glosmp gmpmp gdaismp grpomp gpgomp gcvomp 016 r/w gfeomp gbipomp gvaismp glopmp grfimp gunemp gslmmp grdimp 017 r/w d7p d6p d5p d4p d3p d2p d1p d0p 018 r/w d7p d6p d5p d4p d3p d2p d1p d0p 019 r d7p d6p d5p d4p d3p d2p d1p d0p 01a r/w bdcstp r eprbsap ensrpp r ds1cnp 01b r/w etbrcfp etbrsfp etbrpfp r emckfp etbtcfp etbtsfp etbtpfp 01c r/w r r r r etbrpyp eprbsep etbiep etbxep 01d r/w ectl7p ectl6p ectl5p ectl4p ectl3p ectl2p ectl1p ectl0p 01e r/w tblpbkp ftbtpep tbtcip tbrcip tbddp r r rdid10p 01f - 03b - spare 03c r/w dplllkp dpll6p dpll5p dpll4p dpll3p dpll2p dpll1p dpll0p 03d r/w r r r byplbp prbsckp tmdisp c2ph1p c2ph0p 03e r/w=clr tbrckfmp tbrsnfmp tbrpafmp rmckfmp tbtckfmp tbtsnfmp tbtpafmp 03f r/w=clr r r r r tbrpyfmp prbsfmp tbiefmp tbxefmp address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x+00 r/w idle explos datacom enzc lcode encod mode1 mode0 x+01 r/w sh2vais los2ais lof2vais crc6 vais2ais rfi2yel yel2rfi ais2vais x+02 r/w srdi-vpd srdi-vsd srdi-vcd r rdiis slm2ais febeis une2ais x+03 r/w sfebe sdaiss sbipe r sdaisl syell srfi svtais x+04 r/w tbrval tel bus rx sts-1 number (1-3) tel bus rx vt group or tug number (1-7) tel bus rx vt or tu number (1-4) x+05 r/w tbtval tel bus tx sts-1 number (1-3) tel bus tx vt group or tug number (1-7) tel bus tx vt or tu number (1-4) x+06 r/w pl8 pl7 pl6 pl5 pl4 pl3 pl2 pl1 address (hex) mode* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 100 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+07 r/w r expected signal label (2-0) r transmit signal label (2-0) x+08 r/w xpm dmpm losm mpm daism rpom pgom cvom x+09 r/w feom bipom vaism lopm rfim unem slmm rdim x+0ar/wr rrrr rdi-vpdm rdi-vsdm rdi-vcdm x+0b r/w r r r ringen r r r r x+0c r/w dtlpbk dflpbk rstch sprbs r r r r x+0d - x+0f - reserved x+10 r xps dmps loss mps daiss rpos pgos cvos x+11 r feos bipos vaiss lops rfis unes slms rdi-vs x+12rr rrrr rdi-vpds rdi-vsds rdi-vcds x+13 - spare x+14 r/w=clr xpe dmpe lose mpe daise rpoe pgoe cvoe x+15 r/w=clr feoe bipoe vaise lope rfie unee slme rdi-ve x+16 r/w=clr r r r r r rdi-vpde rdi-vsde rdi-vcde x+17 - spare x+18 r/w=clr xppm dmppm lospm mppm daispm rpopm pgopm cvopm x+19 r/w=clr feopm bipopm vaispm loppm rfipm unepm slmpm rdi-vpm x+1a r/w=clr r r r r r rdi-vpdpm rdi-vsdpm rdi-vcdpm x+1b - spare x+1c r/w=clr xpfm dmpfm losfm mpfm daisfm rpofm pgofm cvofm x+1d r/w=clr feofm bipofm vaisfm lopfm rfifm unefm slmfm rdi-vfm x+1e r/w=clr r r r r r rdi-vpdfm rdi-vsdfm rdi-vcdfm x+1f - spare x+20 r shdais shyel r rxss1 rxss0 received signal label (2-0) x+21 - spare x+22 r/w=clr cvc7 cvc6 cvc5 cvc4 cvc3 cvc2 cvc1 cvc0 x+23 r/w=clr r r r r cvc11 cvc10 cvc9 cvc8 x+24 r/w=clr count of pointer increments received count of pointer decrements received x+25 r/w=clr count of pointer increments generated count of pointer decrements generated x+26 r/w=clr bec7 bec6 bec5 bec4 bec3 bec2 bec1 bec0 x+27 r/w=clr r r r r bec11 bec10 bec9 bec8 x+28 r/w=clr fec7 fec6 fec5 fec4 fec3 fec2 fec1 fec0 x+29 r/w=clr r r r r fec11 fec10 fec9 fec8 x+2a r/w lcvc7 lcvc6 lcvc5 lcvc4 lcvc3 lcvc2 lcvc1 lcvc0 address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 101 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+2b r/w r r r r lcvc11 lcvc10 lcvc9 lcvc8 x+2c r/w latched count of pointer increments received latched count of pointer decrements received x+2d r/w latched count of pointer increments generated latched count of pointer decrements generated x+2e r/w lbec7 lbec6 lbec5 lbec4 lbec3 lbec2 lbec1 lbec0 x+2f r/w r r r r lbec11 lbec10 lbec9 lbec8 x+30 r/w lfec7 lfec6 lfec5 lfec4 lfec3 lfec2 lfec1 lfec0 x+31 r/w r r r r lfec11 lfec10 lfec9 lfec8 x+32 r rxob7-rxob0 (rx o-bits) x+33 r rxj27-rxj20 (rx j2) x+34 r rxz67-rxz60 (rx z6/n2) x+35 r rxz77-rxz70 (rx z7/k4) x+36 r/w txob7-txob0 (tx o-bits) x+37 r/w txj27-txj20 (tx j2) x+38 r/w txz67-txz60 (tx z6/n2) x+39 r/w txz77-txz70 (tx z7/k4) x+3a r r r r r rgfebe-v rgrdi-vpd rgrdi-vsd rgrdi-vcd x+3b - x+3f reserved address (hex) mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - 102 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers memory map descriptions common memory map four groups of common memory blocks are provided, as described above, each controlling a group of 7 chan- nels. component id (p = 1 - 4) global registers (p = 1 - 4) address bit symbol description 000 7-0 mi7p-mi0p manufacturer identity: read-only register containing the seven least significant bits of the component manufacturer ? s identity (107 decimal) followed by a 1 in bit 0 (d7 hex). 001 7-4 pn3p-pn0p part number: read-only register containing the four least significant bits of the component part number (9 hex). 3-0 mi11p-mi8p manufacturer identity: read-only register containing the four most sig- nificant bits of the component manufacturer ? s identity (0 hex). 002 7-0 pn11p-pn4p part number: read-only register containing the middle eight bits of the component part number (06 hex). 003 7-4 v3p-v0p version: read-only register containing the component version number (2 hex). 3-0 pn15p-pn12p part number: read-only register containing the four most significant bits of the component part number (1 hex). 004 7-0 notebook(p) user register: read/write register for end-user application. the content of this register will have no effect on the operation of the device. 005 7-0 resetp software reset: writing a 91 hex into this location will generate a soft- ware reset to a group of 7 channels (all but configuration registers are reset). writing other than 91 hex will remove a group of 7 channels from the reset state. reading this location will return a 00 hex if a group of 7 channels is not in reset and 01 hex if a group of 7 channels is in reset. the t1mx28 will default to reset on application of external hardware reset (rsti ). address bit symbol description 006 7 simp sectional interrupt mask: when cleared (this bit set to zero), the exter- nal interrupt outputs (leads intop/irqop ) will be asserted when an internal interrupt event occurs to a group of 7 channels (p = 1 - 4). the internal interrupt status may still be polled by software to detect interrupt events when this bit is set to one. 6risep rising edge interrupt: when set to one, a status change will be regis- tered as a one in the latched value bits on the start of an event. 5fallp falling edge interrupt: when set to one, a status change will be regis- tered as a one in the latched value bits on the end of an event. - 103 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 006 (cont.) 4ipolp interrupt polarity: when set to one, the polarity of the interrupt lead will be inverted at the lead. 3enpmfmp enable pm/fm function: when set to one, the performance and fault monitoring function is in the pm/fm registers (00e/f, 03e/f, x+18h to x+1eh) and the latched counters (x+2ah to x+31h); latching takes place after t1si rising edge. both risep and fallp must be set to one. 2 enhwmp enable hardware mask: when set to one, global errors (e.g., adclk (bdclk) fails; tbrcksp = 1) may be used to generate an active low internal alarm output on leads aiao (for p = 1 and 2) or biao (for p = 3 and 4), if enabled (e.g., control bit etbrcfp = 1). when set to zero, leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) will remain high. 1-0 r reserved: these bits must be set to zero. 007 7 tcaep tributary transmit clock active edge: if this bit is set to one, the tposn, tnegn/tsigln and tsyncn signals are clocked out of the a group of 7 channels on the rising edge of ltclkn. when set to zero, they are clocked out on the falling edge of ltclkn. 6rcaep tributary receive clock active edge: if this bit is set to one, the rposn, rnegn/rsigln/rcvn and rsyncn signals are clocked into a group of 7 channels on the rising edge of lrclkn and out of a group of 7 channels on the falling edge of lrclkn. when set to zero, they are clocked in or out on the falling/rising edge of lrclkn respectively. 5 sdhp sdh functions: when this bit is set to one, the pointer tracking state machine will transition from the ais state to the lop state on receipt of eight invalid pointers and a block count of bip-2 errors will be recorded by the bip-2 error counter. this is used in sdh applications. when set to zero, the pointer tracking state machine will not include the ais state to the lop state transition and the actual number of bip-2 errors will be recorded by the bip-2 error counter. this setting is used in sonet appli- cations. 4 rxnrzpp receive nrz polarity: when set to one, the polarity of the data received at rposn and laisn for a group of 7 channels will be inverted at these leads; a low will be interpreted as a logic one. 3tbpisp telecom bus parity includes sync.: when set to one, the signals aac1j1v1(bac1j1v1) and aaspe(baspe) are included with aad(0-7) (bad(0-7)) in the parity calculation for aapar(bapar). when set to zero, aapar(bapar) includes parity calculated for aad(0-7)(bad(0-7)) only. for dual bus applications, the control bits must be set to the same value for channels 1 through 14 as a group (for p = 1 and 2) and chan- nels 15 through 28 as a group (for p = 3 and 4). for single bus applica- tions the control bits must be set to the same value for all channels (for p = 1 - 4). address bit symbol description - 104 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 007 (cont.) 2 tbpep telecom bus parity even/odd: when set to one, even parity is calcu- lated for aapar(bapar) and checked for adpar(bdpar). when set to zero, odd parity is calculated for aapar(bapar) and checked for adpar(bdpar). for dual bus applications, the control bits must be set to the same value for channels 1 through 14 as a group (for p = 1 and 2) and channels 15 through 28 as a group (for p = 3 and 4). for single bus applications the control bits must be set to the same value for all chan- nels (for p = 1 - 4). 1vc3vc4p vc3/vc4 telecom bus operation: when set to one, the telecom bus operates with stuffing per sonet requirements and sdh requirements for a tu-11 in a tug-2, vc-3, au-3 at either 6.48 or 19.44 mhz. when set to zero, the telecom bus operates with stuffing per sdh require- ments for a tu-11 in a tug-2 via a tug-3, vc-3, au-4 at 19.44 mhz only. lead configi must be set to low if sdh stuffing is required. for dual bus applications, the control bits must be set to the same value for channels 1 through 14 as a group (for p = 1 and 2) and channels 15 through 28 as a group (for p = 3 and 4). for single bus applications the control bits must be set to the same value for all channels (for p = 1 - 4). 0 txnrzpp transmit nrz polarity: when set to one, the polarity of the data trans- mitted at tposn will be inverted at the lead for a group of 7 channels; a logic one will generate a low output signal. 008 7 mtbrcfp mask telecom bus receive clock fail: when set to one, the fault detector for adclk (for p = 1 and 2) or bdclk (for p = 3 and 4) is masked from generating an interrupt (status and event not affected). 6 mtbrsfp mask telecom bus receive sync. fail: when set to one, the fault detector for adc1j1v1 (for p = 1 and 2) or bdc1j1v1 (for p = 3 and 4) is masked from generating an interrupt (status and event not affected). 5 mtbrpfp mask telecom bus receive payload indicator fail: when set to one, the fault detector for adspe (for p = 1 and 2) or bdspe (for p = 3 and 4) is masked from generating an interrupt (status and event not affected). 4r reserved: this bit must be set to zero. 3mmckfp mask master clock fail: when set to one, the fault detector for srclk is masked from generating an interrupt (status and event not affected). 2 mtbtcfp mask telecom bus transmit clock fail: when set to one, the fault detector for aaclk (for p = 1 and 2) or baclk (for p = 3 and 4) is masked from generating an interrupt (status and event not affected). 1 mtbtsfp mask telecom bus transmit sync. fail: when set to one, the fault detector for aac1j1v1 (for p = 1 and 2) or bac1j1v1 (for p = 3 and 4) is masked from generating an interrupt (status and event not affected). 0 mtbtpfp mask telecom bus transmit payload indicator fail: when set to one, the fault detector for aaspe (for p = 1 and 2) or baspe (for p = 3 and 4) is masked from generating an interrupt (status and event not affected). address bit symbol description - 105 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 009 7-4 r reserved: these bits must be set to zeros. 3mtbrpyp mask telecom bus receive parity error: when set to one, the parity error detector for the received telecom bus is masked from generating an interrupt (status and event not affected). 2 mprbsep mask prbs out of lock events: when set to one, the prbs analyzer out of lock output for a group of 7 channels is masked from generating an interrupt (status and event not affected). 1mtbiep mask telecom bus internal error: when set to one, the fault detector for telecom bus transmit internal collisions is masked from generating an interrupt (status and event not affected). 0mtbxep mask telecom bus external error: when set to one, the fault detector for telecom bus transmit external collisions is masked from generating an interrupt (status and event not affected). 00a 7 tbrcksp telecom bus receive clock fail status: when set to one, the fault detector for adclk (for p = 1 and 2) or bdclk (for p = 3 and 4) is cur- rently detecting loss of transitions. this bit is set to a 1 when no adclk or bdclk transitions are detected for a time between 32 and 64 cycles of pcki. this bit is cleared to 0 when adclk or bdclk transitions are present for between 32 and 64 cycles of pcki. 6tbrsnsp telecom bus receive sync. fail status: when set to one, the fault detector for adc1j1v1 (for p = 1 and 2) or bdc1j1v1 (for p = 3 and 4) is currently detecting loss of transitions. detection time is 2000 500 microseconds; clear time is a single transition of adc1j1v1 or bdc1j1v1. 5 tbrpasp telecom bus receive payload indicator fail status: when set to one, the fault detector for adspe (for p = 1 and 2) or bdspe (for p = 3 and 4) is currently detecting loss of transitions. minimum detection time is 35 microseconds; clear time is a single transition of adspe or bdspe. 4r reserved: this bit reads out as zero. 3mcksp master clock fail status: when set to one, the fault detector for srclk is currently detecting loss of transitions. detection time is 2.0 0.5 microseconds (32 cycles of pcki @ 16 mhz); this bit is cleared to zero when srclk is present for 32 cycles of pcki. 2tbtcksp telecom bus transmit clock fail status: when set to one, the fault detector for aaclk (for p = 1 and 2) or baclk (for p = 3 and 4) is cur- rently detecting loss of transitions. this bit is set to a 1 when no aaclk or baclk transitions are detected for a time between 32 and 64 cycles of pcki. this bit is cleared to 0 when aaclk or baclk transitions are present for between 32 and 64 cycles of pcki. 1tbtsnsp telecom bus transmit sync. fail status: when set to one, the fault detector for aac1j1v1 (for p = 1 and 2) or bac1j1v1 (for p = 3 and 4) is currently detecting loss of transitions. detection time is 2000 500 microseconds; clear time is a single transition of aac1j1v1 or bac1j1v1. address bit symbol description - 106 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 00a (cont.) 0 tbtpasp telecom bus transmit payload indicator fail status: when set to one, the fault detector for aaspe (for p = 1 and 2) or baspe (for p = 3 and 4) is currently detecting loss of transitions. minimum detection time is 49 microseconds; clear time is a single transition of aaspe or baspe. 00b 7-4 r reserved: these bits read out as zeros. 3 tbrpysp telecom bus receive parity error status: when set to one, the parity error detector for the received telecom bus is detecting a parity error. 2prbssp prbs out of lock status: when set to one, the prbs analyzer is out of lock. 1 tbiesp telecom bus internal error status: when set to one, the fault detector for telecom bus transmit internal collisions is detecting simultaneous bus slot access (i.e., two or more channel registers at x+05h set to same slot). 0tbxesp telecom bus external error status: when set to one, the fault detector for telecom bus transmit external collisions is detecting simultaneous bus slot access as determined by the aaadd(1-2) (for p = 1 and 2) or baadd(1-2) (for p = 3 and 4) and abuschk(1-4) (for p = 1 and 2) or bbuschk(1-4) (for p = 3 and 4) lead levels. 00c 7 tbrckep telecom bus receive clock fail latched event: this bit will be set to one when the active edge, as selected by risep and fallp, has occurred for adclk (for p = 1 and 2) or bdclk (for p = 3 and 4) loss of clock. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 6 tbrsnep telecom bus receive sync. fail latched event: this bit will be set to one when the active edge, as selected by risep and fallp, has occurred for adc1j1v1 (for p = 1 and 2) or bdc1j1v1 (for p = 3 and 4) loss of signal. if not masked, an interrupt and/or internal alarm is gener- ated when this bit is set. this bit is cleared only by writing it to zero. 5tbrpaep telecom bus receive payload indicator fail latched event: this bit will be set to one when the active edge, as selected by risep and fallp, has occurred for adspe (for p = 1 and 2) or bdspe (for p = 3 and 4) loss of signal. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 4r reserved: this bit must be set to zero. 3 mckep master clock fail latched event: this bit will be set to one when the active edge, as selected by risep and fallp, has occurred for srclk loss of clock. if not masked, an interrupt and/or internal alarm is gener- ated when this bit is set. this bit is cleared only by writing it to zero. 2 tbtckep telecom bus transmit clock fail latched event: this bit will be set to one when the active edge, as selected by risep and fallp, has occurred for aaclk (for p = 1 and 2) or baclk (for p = 3 and 4) loss of clock. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. address bit symbol description - 107 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 00c (cont.) 1tbtsnep telecom bus transmit sync. fail latched event: this bit will be set to one when the active edge, as selected by risep and fallp, has occurred for aac1j1v1 (for p = 1 and 2) or bac1j1v1 (for p = 3 and 4) loss of signal. if not masked, an interrupt and/or internal alarm is gener- ated when this bit is set. this bit is cleared only by writing it to zero. 0 tbtpaep telecom bus transmit payload indicator fail latched event: this bit will be set to one when the active edge, as selected by risep and fallp, has occurred for aaspe (for p = 1 and 2) or baspe (for p = 3 and 4) loss of signal. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 00d 7-4 r reserved: these bits must be set to zeros. 3 tbrpyep telecom bus receive parity error latched event: this bit will be set to one when the active edge, as selected by risep and fallp, has occurred for a parity error. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 2prbsep prbs out of lock latched event: this bit will be set to one when the active edge, as selected by risep and fallp, has occurred for a prbs out of lock condition. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 1 tbieep telecom bus internal error latched event: this bit will be set to one when the active edge, as selected by risep and fallp, has occurred for an internal bus error. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 0 tbxeep telecom bus external error latched event: this bit will be set to one when the active edge, as selected by risep and fallp, has occurred for an external bus error. if not masked, an interrupt and/or internal alarm is generated when this bit is set. this bit is cleared only by writing it to zero. 00e 7 tbrckpmp telecom bus receive clock performance monitor: this bit will be set to one if adclk (for p = 1 and 2) or bdclk (for p = 3 and 4) loss of clock has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrckep has been cleared. 6 tbrsnpmp telecom bus receive sync. performance monitor: this bit will be set to one if adc1j1v1 (for p = 1 and 2) or bdc1j1v1 (for p = 3 and 4) loss of signal has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrsnep has been cleared. 5tbrpapmp telecom bus receive payload indicator performance monitor: this bit will be set to one if adspe (for p = 1 and 2) or bdspe (for p = 3 and 4) loss of signal has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si ris- ing edge if the condition no longer exists and event bit tbrpaep has been cleared. address bit symbol description - 108 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 00e (cont.) 4r reserved: this bit must be set to zero. 3mckpmp master clock performance monitor: this bit will be set to one if srclk loss of clock has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit mckep has been cleared. 2 tbtckpmp telecom bus transmit clock performance monitor: this bit will be set to one if aaclk (for p = 1 and 2) or baclk (for p = 3 and 4) loss of clock has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbtckep has been cleared. 1 tbtsnpmp telecom bus transmit sync. performance monitor: this bit will be set to one if aac1j1v1 (for p = 1 and 2) or bac1j1v1 (for p = 3 and 4) loss of signal has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbtsnep has been cleared. 0 tbtpapmp telecom bus transmit payload indicator performance monitor: this bit will be set to one if aaspe (for p = 1 and 2) or baspe (for p = 3 and 4) loss of clock has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si ris- ing edge if the condition no longer exists and event bit tbtpaep has been cleared. 00f 7-4 r reserved: these bits must be set to zeros. 3 tbrpypmp telecom bus receive parity error performance monitor: this bit will be set to one if a parity error has occurred at any time in the last one-sec- ond interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrpyep has been cleared. 2prbspmp prbs out of lock performance monitor: this bit will be set to one if a prbs out of lock has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si ris- ing edge if the condition no longer exists and event bit prbsep has been cleared. 1tbiepmp telecom bus internal error performance monitor: this bit will be set to one if an internal bus collision has occurred at any time in the last one- second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbieep has been cleared. 0 tbxepmp telecom bus external error performance monitor: this bit will be set to one if an external bus collision has occurred at any time in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbxeep has been cleared. 010 7-0 spare spare: this register should not be accessed. address bit symbol description - 109 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 011 7 r reserved: this bit reads out as zero. 6-0 ch7p - ch1p channel activity: a bit is set to one for any channel in a group that has one or more pending events. it is used as a polling register to identify channels in need of service or to locate channels that have generated an interrupt. 012 7-0 spare spare: this register should not be accessed. 013 7 gxpep global external lais lead event: this bit will be set to one if an active signal is present (xpe is one) in any group of channels for lais. this bit will be cleared when all lais events have been cleared in the individual channel event registers for the group. 6gdmpep global demap error event: this bit will be set to one if a demap error event (dmpe) is present in any group of channels. this bit will be cleared when all demap error events have been cleared in the individual channel event registers for the group. 5glosep global los event: this bit will be set to one if a ds1 loss of signal event (lose) is present in any group of channels. this bit will be cleared when all ds1 loss of signal events have been cleared in the individual channel event registers for the group. 4gmpep global map error event: this bit will be set to one if a map error event (mpe) is present in any group of channels. this bit will be cleared when all map error events have been cleared in the individual channel event registers for the group. 3gdaisep global ds1 ais event: this bit will be set to one if a ds1 ais event (daise) is present in any group of channels. this bit will be cleared when all ds1 ais events have been cleared in the individual channel event registers for the group. 2grpoep global received pointer justification counter overflow event: this bit will be set to one if a received pointer justification counter overflow event (rpoe) is present in any group of channels. this bit will be cleared when all receive pointer counter overflow events have been cleared in the individual channel event registers for the group. 1gpgoep global generated pointer justification counter overflow event: this bit will be set to one if a generated pointer justification counter over- flow event (pgoe) is present in any group of channels. this bit will be cleared when all pointer generation counter overflow events have been cleared in the individual channel event registers for the group. 0gcvoep global code violation counter/crc-6 error counter overflow event: this bit will be set to one if a code violation counter/crc-6 error counter overflow event (cvoe) is present in any group of channels. this bit will be cleared when all code violation counter/crc-6 error counter overflow events have been cleared in the individual channel event regis- ters for the group. address bit symbol description - 110 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 014 7 gfeoep global rei (febe) counter overflow event: this bit will be set to one if a rei (febe) counter overflow event (feoe) is present in any group of channels. this bit will be cleared when all rei (febe) counter overflow events have been cleared in the individual channel event registers for the group. 6 gbipoep global bip-2 error counter overflow event: this bit will be set to one if a bip-2 error counter overflow event (bipoe) is present in any group of channels. this bit will be cleared when all bip-2 error counter overflow events have been cleared in the individual channel event registers for the group. 5 gvaisep global vt ais event: this bit will be set to one if a vt ais event (vaise) is present in any group of channels. this bit will be cleared when all vt ais events have been cleared in the individual channel event reg- isters for the group. 4glopep global loss of pointer event: this bit will be set to one if a loss of pointer event (lope) is present in any of the channels. this bit will be cleared when all loss of pointer events have been cleared in the individ- ual channel event registers for the group. 3grfiep global rfi event: this bit will be set to one if a remote failure indication event (rfie) is present in any group of channels. this bit will be cleared when all rfi events have been cleared in the individual channel event registers for the group. 2 guneep global unequipped event: this bit will be set to one if an unequipped event (unee) is present in any group of channels. this bit will be cleared when all unequipped events have been cleared in the individual channel event registers for the group. 1gslmep global signal label mismatch event: this bit will be set to one if a sig- nal label mismatch event (slme) is present in any group of channels. this bit will be cleared when all signal label mismatch events have been cleared in the individual channel event registers for the group. 0 grdiep global rdi event: this bit will be set to one if a remote defect indication event (rdi-ve, rdi-vpde, rdi-vsde or rdi-vcde) is present in any group of channels. this bit will be cleared when all rdi events have been cleared in the individual channel event registers for the group. 015 7 gxpmp global external lais lead event mask: when set to one, all per chan- nel lais events (xpe) are masked from generating interrupts (overrides per channel mask when set) for the group. 6gdmpmp global demap error event mask: when set to one, all per channel demap error events (dmpe) are masked from generating interrupts (overrides per channel mask when set) for the group. 5glosmp global los event mask: when set to one, all per channel los events (lose) are masked from generating interrupts (overrides per channel mask when set) for the group. address bit symbol description - 111 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 015 (cont.) 4 gmpmp global map error event mask: when set to one, all per channel map error events (mpe) are masked from generating interrupts (overrides per channel mask when set) for the group. 3gdaismp global ds1 ais event mask: when set to one, all per channel ds1 ais events (daise) are masked from generating interrupts (overrides per channel mask when set) for the group. 2grpomp global received pointer justification counter overflow event mask: when set to one, all received pointer justification counter overflow events (rpoe) are masked from generating interrupts (overrides per channel mask when set) for the group. 1gpgomp global generated pointer justification counter overflow event mask: when set to one, all per channel generated pointer justification counter overflow events (pgoe) are masked from generating interrupts (overrides per channel mask when set) for the group. 0gcvomp global code violation counter/crc-6 error counter overflow event mask: when set to one, all per channel code violation counter/crc-6 error counter overflow events (cvoe) are masked from generating inter- rupts (overrides per channel mask when set) for the group. 016 7 gfeomp global rei (febe) counter overflow event mask: when set to one, all per channel rei (febe) counter overflow events (feoe) are masked from generating interrupts (overrides per channel mask when set) for the group. 6 gbipomp global bip-2 error counter overflow event mask: when set to one, all per channel bip-2 error counter overflow events (bipoe) are masked from generating interrupts (overrides per channel mask when set) for the group. 5gvaismp global vt ais event mask: when set to one, all per channel vt ais events (vaise) are masked from generating interrupts (overrides per channel mask when set) for the group. 4glopmp global loss of pointer event mask: when set to one, all per channel lop events (lope) are masked from generating interrupts (overrides per channel mask when set) for the group. 3grfimp global rfi event mask: when set to one, all per channel rfi events (rfie) are masked from generating interrupts (overrides per channel mask when set) for the group. 2 gunemp global unequipped event mask: when set to one, all per channel unequipped events (unee) are masked from generating interrupts (over- rides per channel mask when set) for the group. 1gslmmp global signal label mismatch event mask: when set to one, all per channel signal label mismatch events (slme) are masked from generat- ing interrupts (overrides per channel mask when set) for the group. 0 grdimp global rdi event mask: when set to one, all per channel rdi events (rdi-ve, rdi-vpde, rdi-vsde or rdi-vcde) are masked from gener- ating interrupts (overrides per channel mask when set) for the group. address bit symbol description - 112 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 017 7-0 d7p-d0p command byte: this register contains the command byte for the serial port for a group of channels. the definitions of the bits will depend on the external device that is selected. the serial port control logic does not depend on the values in this register for operation. this byte is shifted out lsb (d0) first and represents the first byte sent out at leads lsdop. 018 7-0 d7p-d0p line interface serial data output: this register contains the serial data to be written to the selected line interface transceiver for a group of channels. the data is shifted out lsb (d0) first and represents the second byte sent out at leads lsdop. 019 7-0 d7p-d0p line interface serial data input: this register contains the read back data from the line interface transceiver when a read operation is per- formed for a group of channels. the data is shifted in lsb (d0) first (see leads lsdip). 01a 7 bdcstp broadcast: when this bit is set to one, serial port command and data output registers are broadcast to the line interface transceivers for a group of channels. 6r reserved: this bit must be set to zero. 5 eprbsap prbs enable: when set to one, both the internal prbs analyzer and prbs generator are enabled for a group of channels. bits 2, 1 and 0 of this register select which channel ? s line decoder output is connected to the analyzer. the analyzer ? s output is a one for bits prbssp, prbsep, prbspmp and prbsfmp as controlled by bits mprbsep and eprbsep. when this bit is set to zero or when the prbs analyzer is in lock, a zero is present in prbssp, prbsep, prbspmp and prbsfmp. to operate with an itu-t o.151 compliant 2 15 - 1 signal, the output of the prbs generator and/or the input to the prbs analyzer must be inverted. this is controlled by setting either or both txnrzpp and rxnrzpp in the global registers to a 1. 4ensrpp enable serial port: when set to one, a single transfer takes place to the selected device (single or broadcast) in serial port mode for a group of channels. this bit must be toggled to zero before setting it to one for another transfer. 3r reserved: this bit must be set to zero. 2-0 ds1cnp ds1 channel number (0-6): when decoded with bit 0 as least signifi- cant bit the value (n=0-6) selected drives the active low chip select lead, lcs(n+1) . bdcstp causes all lcsn leads to be selected in serial port mode for a group of channels. in prbs operation these bits select the channel in the group to be moni- tored by the prbs analyzer. address bit symbol description - 113 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 01b 7 etbrcfp enable telecom bus receive clock fail: when set to one, the fault detector for adclk (for p = 1 and 2) or bdclk (for p = 3 and 4) is enabled to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) if adclk (for p = 1 and 2) or bdclk (for p = 3 and 4) fails. 6etbrsfp enable telecom bus receive sync. fail: when set to one, the fault detector for adc1j1v1 (for p = 1 and 2) or bdc1j1v1 (for p = 3 and 4) is enabled to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) if adc1j1v1 (for p = 1 and 2) or bdc1j1v1 (for p = 3 and 4) fails. 5etbrpfp enable telecom bus receive payload indicator fail: when set to one, the fault detector for adspe (for p = 1 and 2) or bdspe (for p = 3 and 4) is enabled to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) if adspe (for p = 1 and 2) or bdspe (for p = 3 and 4) fails. 4r reserved: this bit must be set to zero. 3emckfp enable master clock fail: when set to one, the fault detector for srclk is enabled to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) if srclk fails. 2 etbtcfp enable telecom bus transmit clock fail: when set to one, the fault detector for aaclk (for p = 1 and 2) or baclk (for p = 3 and 4) is enabled to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) if aaclk (for p = 1 and 2) or baclk (for p = 3 and 4) fails. 1 etbtsfp enable telecom bus transmit sync. fail: when set to one, the fault detector for aac1j1v1 (for p = 1 and 2) or bac1j1v1(for p = 3 and 4) is enabled to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) or if aac1j1v1 (for p = 1 and 2) or bac1j1v1 (for p = 3 and 4) fails. 0 etbtpfp enable telecom bus transmit payload indicator fail: when set to one, the fault detector for aaspe (for p = 1 and 2) or baspe (for p = 3 and 4) is enabled to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) if aaspe (for p = 1 and 2) or baspe (for p = 3 and 4) fails. 01c 7-4 r reserved: these bits must be set to zeros. 3etbrpyp enable telecom bus receive parity error: when set to one, the parity error detector for the receive telecom bus is enabled to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) if a parity error is detected. 2 eprbsep enable prbs out of lock events: when set to one, the prbs ana- lyzer out of lock output is enabled to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) if the prbs analyzer goes out of lock. 1etbiep enable telecom bus internal error: when set to one, the fault detector for telecom bus transmit internal collisions is enabled to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) if an internal collision occurs. 0etbxep enable telecom bus external error: when set to one, the fault detec- tor for telecom bus transmit external collisions is enabled to drive leads aiao (for p = 1 and 2) or biao (for p = 3 and 4) if an external collision occurs. address bit symbol description - 114 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 01d 7-0 ectl7p - ectl0p error control length: these bits meter the number of bip-2 or rei (febe) errors introduced when a channel ? s sfebe or sbipe bit (in a group of channels) is set to one. note that when a channel is set to idle (control bit idle is zero), this register has no effect on sfebe or sbipe and sfebe set to one or sbipe set to one will cause continuous rei-v (febe) or bip-2 errors to be sent. 01e 7 tblpbkp telecom bus loopback: when set to one, internally the telecom bus is placed in loopback with all 28 or 84 timeslots out of the mappers con- nected to the 28 or 84 timeslots of the demappers. aaclk (for p = 1 and 2) or baclk (for p = 3 and 4) is the only telecom bus signal used in telecom bus loopback; payload and reference signals are internally generated. this is an off-line test for the entire t1mx28 with invalid data sent to the telecom bus; individual channels may be tested with the prbs generator/analyzer in this mode. 6ftbtpep force telecom bus transmit parity error: when set to one, the parity to the telecom bus (aapar (for p = 1 and 2) or bapar (for p = 3 and 4)) is inverted, forcing continuous parity errors. 5tbtcip telecom bus transmit clock inversion: this controls the active edge of the add bus clock (aaclk for p = 1 and 2) or (baclk for p = 3 and 4). when set to zero, the add bus input signals aaspe (for p = 1 and 2) or baspe (for p = 3 and 4) and aac1j1v1 (for p = 1 and 2) or bac1j1v1 (for p = 3 and 4) are sampled on the rising edge of aaclk (for p = 1 and 2) or baclk (for p = 3 and 4). the aad(0-7) aapar and aaadd(1-2) output signals and clocked out to the "a" add bus on the falling edge of aaclk (for p = 1 and 2). the bad(0-7), bapar and baadd(1-2) output signals are clocked out to the "b" add bus on the falling edge of baclk (for p = 3 and 4). when set to one, aaspe (for p = 1 and 2) or baspe (for p = 3 and 4) and aac1j1v1 (for p = 1 and 2) or bac1j1v1 (for p = 3 and 4) are sam- pled on the falling edge of aaclk (for p = 1 and 2) or baclk (for p = 3 and 4). aad(0-7), aapar and aaadd(1-2) are clocked out on the rising edge of aaclk (for p = 1 and 2). bad(0-7), bapar and baadd(1-2) are clocked out on the rising edge of baclk (for p = 3 and 4). 4 tbrcip telecom bus receive clock inversion: when set to zero, the active edge of adclk (for p = 1 and 2) or bdclk (for p = 3 and 4) is the rising edge. when set to one, the active edge of adclk (for p = 1 and 2) or bdclk (for p = 3 and 4) is the falling edge. address bit symbol description ectl7p-ectl0p resulting errors sent 00 1 frame 01 2 frames 02 3 frames fd 254 frames fe 255 frames ff continuous - 115 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 01e (cont.) 3tbddp telecom bus data delay: when set to zero, aad(0-7) (for p = 1 and 2) or bad(0-7) (for p = 3 and 4) and aapar (for p = 1 and 2) or bapar (for p = 3 and 4) are pre-fetched and made available on the active edge of aaclk (for p = 1 and 2) or baclk (for p = 3 and 4) as defined by aaspe (for p = 1 and 2) or baspe (for p = 3 and 4) and aac1j1v1 (for p = 1 and 2) or bac1j1v1 (for p = 3 and 4) (as shown in figure 10 and figure 11) with drive control as determined by drive leads adaten (for p = 1 and 2) or bdaten (for p = 3 and 4) and mastera (masterb ) (as described in the block diagram description and operation-telecom bus interface section). when set to one, aad(0-7) (for p = 1 and 2) or bad(0- 7) (for p = 3 and 4) and aapar (for p = 1 and 2) or bapar (for p = 3 and 4) are delayed by one full clock period of aaclk (for p = 1 and 2) or baclk (for p = 3 and 4); adaten (for p = 1 and 2) or bdaten (for p = 3 and 4) inputs must be delayed externally by one aaclk or baclk period if they are to be used (e.g., adaten or bdaten controlled by aaspe or baspe). 2-1 r reserved: these bits must be set to zeros. 0 rdid10p rdi de-bouncing equals 10: when set to zero, rdi is de-bounced for 5 vt superframes for a group of channels. this means it must be set for 5 vt superframes in a row to be declared as rdi for a channel and it must be cleared for 5 vt superframes in a row to be cleared. when set to one, rdi is de-bounced for 10 vt superframes for a group of channels. 01f - 03b 7-0 spare spare: these registers should not be accessed. 03c 7 dplllkp digital phase lock loop lock: when set to one, the dpll fifo depth is determined by the value of dpll6p-dpll0p in this register. this forces a constant frequency from all dplls (ltclkn). when set to zero, the dpll bias offset is determined by dpll6p-dpll0p. for normal t1mx28 operation set dplllkp to zero. this control bit is for test pur- poses. 6-0 dpll6p - dpll0p digital phase lock loop control: when dplllkp is set to zero, the value of dpll6p-dpll0p is the ones complement of the dpll bias off- set; for dpll6p-dpll0p = 00 hex, the nominal design value is chosen. when dplllkp is set to one, dpll6p-dpll0p determines the fifo depth. for normal operation, set to zero. these control bits are for test purposes. 03d 7-5 r reserved: these bits must be set to zeros. 4 byplbp bypass pointer leak buffer: when set to zero, the pointer leak buffer is enabled in all channels. when set to one, the pointer leak buffer is bypassed. for normal operation, set this bit to zero. this control bit is for test purposes. 3prbsckp prbs clock: when set to zero, srclk is selected as the source of prbs clock. this bit is used for manufacturing tests; do not set it to a 1. 2tmdisp threshold modulator disable: when set to zero, the threshold modula- tor is enabled. when set to one, the threshold modulator is disabled. for normal operation this bit should be set to zero. this control bit is for test purposes and may not be available in future versions. address bit symbol description - 116 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 03d (cont.) 1-0 c2ph1p- c2ph0p c2 stuff bit phase: when both bits are set to zero, normal threshold modulator phase is chosen for the c2 stuff bits. setting either or both of these bits to one chooses an alternate phase for the threshold modula- tor. for normal operation, both of these bits should be set to zero. these control bits are for test purposes and may not be available in future ver- sions. 03e 7 tbrckfmp telecom bus receive clock fault monitor: this bit will be set to one if adclk (for p = 1 and 2) or bdclk (for p = 3 and 4) loss of clock is present but the transition to this state did not occur in the last one-sec- ond interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrckep has been cleared. 6tbrsnfmp telecom bus receive sync. fault monitor: this bit will be set to one if adc1j1v1 (for p = 1 and 2) or bdc1j1v1 (for p = 3 and 4) loss of signal is present, but the transition to this state did not occur in the last one-sec- ond interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrsnep has been cleared. 5tbrpafmp telecom bus receive payload indicator fault monitor: this bit will be set to one if adspe (for p = 1 and 2) or bdspe (for p = 3 and 4) loss of signal is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrpaep has been cleared. 4r reserved: this bit must be set to zero. 3mckfmp master clock fault monitor: this bit will be set to one if srclk loss of clock is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit mckep has been cleared. 2tbtckfmp telecom bus transmit clock fault monitor: this bit will be set to one if aaclk (for p = 1 and 2) or baclk (for p = 3 and 4) loss of clock is present, but the transition to this state did not occur in the last one-sec- ond interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbtckep has been cleared. 1tbtsnfmp telecom bus transmit sync. fault monitor: this bit will be set to one if aac1j1v1 (for p = 1 and 2) or bac1j1v1 (for p = 3 and 4) loss of sig- nal is present, but the transition to this state did not occur in the last one- second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbtsnep has been cleared. address bit symbol description - 117 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers 03e (cont.) 0tbtpafmp telecom bus transmit payload indicator fault monitor: this bit will be set to one if aaspe (for p = 1 and 2) or baspe (for p = 3 and 4) loss of clock is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbtpaep has been cleared. 03f 7-4 r reserved: these bits must be set to zeros. 3tbrpyfmp telecom bus receive parity error fault monitor: this bit will be set to one if a parity error is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbrpyep has been cleared. 2prbsfmp prbs out of lock fault monitor: this bit will be set to one if a prbs out of lock is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit prbsep has been cleared. 1 tbiefmp telecom bus internal error fault monitor: this bit will be set to one if an internal bus collision is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbieep has been cleared. 0 tbxefmp telecom bus external error fault monitor: this bit will be set to one if an external bus collision is present, but the transition to this state did not occur in the last one-second interval as defined by t1si. this bit is cleared by writing it to zero or by t1si rising edge if the condition no longer exists and event bit tbxeep has been cleared. address bit symbol description - 118 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers per channel control registers *note: in the address, x= 040h for ds1 channel #1; 080h for ds1 channel #2; 0c0h for ds1 channel #3; 100h for ds1 channel #4; 140h for ds1 channel #5; 180h for ds1 channel #6; 1c0h for ds1 channel #7 of a group. the group is selected by leads selip , where p selects the group of channels (p=1 selects channels 1-7, p=2 selects channels 8-14, p=3 selects channels 15-21 and p=4 selects channels 22-28). address* bit symbol description x+00 7 idle set the channel to idle: when set to zero, the channel is powered down; all-zeros are substituted for the payload and overhead bytes except v5. either an all-zeros v5 may be sent, indicating an unequipped condition, or a valid v5 may be sent (unassigned); v5 is determined by per channel con- trol bits rdiis, febeis, sfebe, srdi and transmit signal label. for nor- mal operation, including sending vt ais, this bit should be set to one. note that for proper idle operation register txz7 (reg. x+39h) should also be set to 00h. 6explos external lead enables los: when set to one, lais active (as determined by rxnrzpp) is treated as los from the decoder. set this bit to one if using an external decoder or external loss of clock detector. set this bit to zero if lais lead is unused or used for another purpose (e.g., interrupt from an external line transceiver). see sh2vais and los2ais below for logic (register x+01h). 5datacom datacom mode: this bit, in conjunction with mode0 and mode1, enables datacom mode. if mode1 is set to zero, this bit is disregarded. see mode0, mode1 in this register. 4enzc enable excess zeros count: when set to one, this bit will enable the bpv counter to also count excess zeros. when b8zs transcoding is enabled, 8 or more consecutive zeros is an error. when b8zs transcoding is disabled, 16 or more consecutive zeros is an error. 3 lcode line code select: when set to one and encod is set to one, b8zs is selected for coding and decoding. when set to zero and encod is set to one, ami is selected for coding and decoding. when encod is set to zero, this bit selects the signal level on tnegn. 2 encod enable codec: when set to one, the line coder and decoder are enabled if mode1 is set to zero with the code selected by lcode. when set to zero, or if mode1 is set to one, nrz is selected. encod lcode mode1 line code tnegn 1 0 0 ami per codec 1 1 0 b8zs per codec 0 0 0,1 nrz logic low 0 1 0,1 nrz logic high - 119 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+00 (cont.) 1 0 mode1, mode0 mode of operation: these bits select among two byte-synchronous or datacom modes and the asynchronous mode. modified byte-synchronous/ datacom mode accepts clock and frame from the framer; in byte-synchro- nous/datacom mode, t1mx28 supplies clock and frame for both directions of transmission. x+01 7 sh2vais enable signaling highway to vt ais: when set to one and datacom set to zero, the ais bit on the signaling highway (rsigln) in byte-synchronous mode maps to vt ais. 6los2ais enable los to vt or ds1 ais: when set to one, los from the ds1 side maps to vt ais (byte-synchronous; see sh2vais for logic) or ds1 ais. address* bit symbol description mode1 mode0 datacom line code mapping mode 0 0 - ami, b8zs, nrz asynchronous 0 1 - ami, b8zs, nrz asynchronous 1 0 0 nrz byte-synchronous 1 0 1 nrz byte-synchronous datacom 1 1 0 nrz modified byte-synchronous 1 1 1 nrz modified byte-synchronous datacom svtais =1 send vt ais + (send vt ais) mode1 (not async mode) los2ais (los to ais) explos (lais = los) lead lias rsigl ais bits = sh2vais (ais = sig hwy) datacom (not datacom mode) ais2vais (ds1 ais to vt a s) ds1 ais (from decoder) mode0 (modified byte sync) loss of frame on rsync lof2vais (lof to vt ais & map error) =1 =1 =1 =1 =1 =0 =1 =1 =1 xpfm, xppm shdais = 1 daisfm, daispm =1 mpfm, mppm 1 & & & + + & & & =1 & / + && 1 =1 xps, xpe, daiss, daise, mps, mpe, legend: & = logical "and" + = logical "or" / = logical "not" mode1 = 0 (async.) + & explos = 1 (lais = los) & xps, xpe, los (from decoder) = 1 & encod = 1(decoder enabled) & + los2ais = 1 (los to ais) & / ds1 ais (from decoder) = 1 loss,lose, daiss, daise, sdaiss = 1 (send ds1 ais to system) send all-ones for ds1 info bits in vt lais lead high xpfm, xppm = 1 losfm, lospm = 1 daisfm, daispm = 1 - 120 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+01 (cont.) 5lof2vais enable loss of frame to vt ais and map error: when set to one, the loss of multiframe synchronization signal (rsyncn) maps to vt ais and is indicated as a map error (see sh2vais for logic). 4 crc6 enable crc-6 generation: when set to one in the true byte sync mode only, crc-6 is generated into the transmit vt payload. crc-6 is calculated on the received vt payload and compared with the received crc-6 code. 3 vais2ais enable vt ais to ds1 ais: when set to one, vt ais received in v1 and v2 is mapped to ds1 ais. 2rfi2yel enable rfi to ds1 yellow: when set to one, rfi received in v5 is mapped to ds1 yellow on the signaling highway. if datacom is set to one, this bit is disregarded. 1yel2rfi enable ds1 yellow to rfi: when set to one, ds1 yellow on the signaling highway maps to rfi in v5 (see rfi2yel for logic). if datacom is set to one, this bit is disregarded. address* bit symbol description datacom =0 ais bits (not datacom mode) mode1 (not async mode) sdaisl (send ds1 ais to line) va is 2 ai s (vt ais to ds1 ais) vt ais vt lop slm2ais (sig lbl mis to ds1 ais) sig lbl mis une2ais (unequip to ds1 ais) =1 =1 =1 =1 =1 =1 vaisfm, vaispm lops, lope, =1 & & + + =1 vaiss, vaise =1 uneq sig lbl signal fail tbrval (telecom bus rx slot not assigned) =1 =0 unefm, unepm =1 unes, unee send ds1 idle =0 =1 & (all-zeros to ds1 line) / & & & & & & / + lopfm, loppm =1 slms, slme, slmfm, slmpm + + tsigl =1 all-ones ds1 signal send ds1 ais srfi =1 (send rfi) yel2rfi (ds1 yellow to rfi) rsigl yellow bit mode1 (not async mode) =1 =1 =1 =1 =1 datacom (not datacom mode) rfi in rec v5 signal fail =0 =1 =1 =1 =0 send rfi vtais =0 shyel = 1 rfi2yel (rfi to ds1 yellow) syell (send ds1 yellow to line) =1 =1 =1 =1 & (tsigl yellow bit = 1) rfis, rfie, send ds1 yellow & & & & & + + (v5 bit 4 = 1) rfifm, rfipm = 1 - 121 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+01 (cont.) 0ais2vais enable ds1 ais to vt ais: when set to one, ds1 ais detected in the decoder (99.9% or more ones) maps to vt ais in the byte sync. mode (see sh2vais for logic). if datacom is set to one, this bit is disregarded. x+02 7 srdi-vpd* send rdi-vpd: when set to one, rdi-vpd is sent continuously if rdiis is also set to one. see rdiis below for logic. set to zero if this channel is pro- grammed unequipped. 6 srdi-vsd* send rdi-vsd: when set to one, rdi-vsd is sent continuously if rdiis is also set to one. see rdiis below for logic. set to zero if this channel is pro- grammed unequipped. 5 srdi-vcd* send rdi-vcd: when set to one, rdi-vcd is sent continuously if rdiis is also set to one. see rdiis below for logic. set to zero if this channel is pro- grammed unequipped. 4r reserved: this bit must be set to zero. 3 rdiis rdi insert select: when set to zero, rdi-vxx is generated autonomously from either internally detected faults or from values input at the ring port. when set to one rdi-vxx is sent continuously if srdi-vxx is set to one. set to one if this channel is programmed unequipped. 2slm2ais enable signal label mismatch to ais: when set to one, a signal label mismatch detected maps to ds1 ais (see vais2ais above for logic). this bit should be set to one if this channel is programmed unequipped. * note:when forcing by microprocessor selection, set only one of the bits srdi-vpd, srdi-vsd and srdi-vcd to one at any given time, to retain proper alarm priority. address* bit symbol description signal fail =0 sig. lbl mismatch srdi-vpd vtais vtlop srdi-vsd sig lbl unequip. srdi-vcd =1 =1 =1 =1 =1 =1 1 ringen =1 rdiis =1 (input) rgrdi-vpd rgrdi-vsd (input) (input) rgrdi-vcd =1 & & & & & & & + & & & & + & / + / & + / / & + & + & + / / / & no defect "0:001" rdi-vpd "0:010" rdi-vsd "1:101" rdi-vcd "1:110" + rgrdi-vpd (output) rgrdi-vsd (output) rgrdi-vcd (output) v5 bit 8 z7 bits 5, 6, 7 in map dir. note: ? w:xyz ? = v5, bit 8: z7, bits 5, 6, 7 - 122 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+02 (cont) 1febeis rei (febe) insert select: when set to zero, rei (febe) is generated from received bip-2 errors or from the ring port input. when set to one, rei (febe) or bip-2 errors can be created with sfebe or spibe. the required rei (febe) value is always output at the ring port (rgfebe-v). the rei (febe) value appearing in the outgoing v5, bit 3 results from received bip-2 errors if ringen is set to zero or from the input ring port value, rgfebe-v, if ringen is set to one. 0 une2ais enable unequipped to ds1 ais: when set to one, an unequipped signal label received is mapped to ds1 ais (see vais2ais for logic). this bit should be set to a zero if this channel is unequipped. use sdais to force ais to ds1 line if required when une2ais is set to zero. x+03 7 sfebe send rei (febe): when set to one, rei (febe) is sent the number of times specified by ectl7p-ectl0p if control bit febeis is set to one, con- trol bit idle is set to one and if control bit ringen is set to zero. when set to one, rei (febe) is sent continuously if control bit febeis is set to one, control bit idle is set to zero and if control bit ringen is set to zero. if ringen is set to one, the febes from the ring port are placed in the out- going v5, bit 3. 6sdaiss send ds1 ais to system: when set to one, ds1 ais (all-ones) is used for the vt1.5 or tu-11 payload in the map direction. 5 sbipe send bip-2 errors: when set to one, inverted bip-2 is sent the number of times specified by ectl7p-ectl0p if febeis is set to one. this bit must be cleared to zero and set again to send a second set of inverted bip-2. 4r reserved: this bit must be set to zero. 3sdaisl send ds1 ais to the ds1 line: when set to one, ds1 ais is sent out of the coder using nominal timing (derived from srclk by dividing by 31.5) 2syell send ds1 yellow: when set to one, ds1 yellow is sent on the signaling highway (tsigln) in byte-synchronous mode. if datacom is set to one, this bit is disregarded. 1srfi send rfi: when set to one, the rfi bit is set in v5. 0 svtais send vt ais: when set to one, vt ais is generated in the mapping direc- tion by generating an all-ones vt1.5 or tu-11. address* bit symbol description febeis =1 sbipe =1 bip-2 error & insert bip-2 in map dir. & increment bec0-bec11 signal fail =0 sfebe =1 ringen =1 rgfebe-v (input) & & + / rgfebe-v (output) & & / + v5, bit 3 in map dir. - 123 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+04 7 tbrval telecom bus receive valid: when set to one, the telecom bus receive slot (information to add(0-7) (for p = 1 and 2) or bdd(0-7) (for p = 3 and 4)), as defined by the rest of the bits in this register, is considered valid and this channel ? s vt1.5 or tu-11 reads the bus. when set to zero, this channel does not read the add(0-7) (for p = 1 and 2) or bdd(0-7) (for p = 3 and 4) bus. 6-5 tel bus rx sts-1 # (1-3) telecom bus receive sts-1 number: these bits select the sts-1 if the configi lead is grounded. 4-2 tel bus rx vt group or tug # (1-7) telecom bus receive vt group or tug number: these bits select the vt group or tug. 1-0 tel bus rx vt or tu # (1-4) telecom bus receive vt or tu number: these bits select the individual vt or tu in the group or tug. address* bit symbol description bit 6 bit 5 sts-1 number 00 1 01 2 10 3 1 1 not valid - do not use bit 4 bit 3 bit 2 vt group or tug number 000 1 001 2 010 3 011 4 100 5 101 6 110 7 1 1 1 not valid - do not use bit 1 bit 0 vt or tu number 00 1 01 2 10 3 11 4 - 124 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+05 7 tbtval telecom bus transmit valid: when set to one, the telecom bus transmit slot (information from aad(0-7) (for p = 1 and 2) or bad(0-7) (for p = 3 and 4)), as defined by the rest of the bits in this register, is considered valid and this channel ? s vt1.5 or tu-11 drives the bus. when set to zero, this chan- nel does not drive the aad(0-7) (for p = 1 and 2) or bad(0-7) (for p = 3 and 4) bus. 6-5 tel bus tx sts-1 # (1-3) telecom bus transmit sts-1 number: these bits select the sts-1 if the configi lead is grounded. 4-2 tel bus tx vt group or tug # (1-7) telecom bus transmit vt group or tug number: these bits select the vt group or tug. 1-0 tel bus tx vt or tu # (1-4) telecom bus transmit vt or tu number: these bits select the individual vt or tu in the group or tug. address* bit symbol description bit 6 bit 5 sts-1 number 00 1 01 2 10 3 1 1 not valid - do not use bit 4 bit 3 bit 2 vt group or tug number 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 1 bit 1 bit 0 vt or tu number 00 1 01 2 10 3 11 4 - 125 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+06 7-0 pl8-pl1 pointer leak rate: these bits determine the rate at which a pointer move- ment is leaked out of the pointer leak buffer into the dpll. if pl8-pl1) is set to 00h the maximum leak rate of one bit per 16 vt superframes (8 ms) is used, with each count decreasing the rate by 16 vt superframes (8 ms). the times shown in the table below apply when the pointer leak buffer (which is 40 bits) is 12 bits or more above or below center. when the pointer leak buffer is less than 12 bits above or below center, the time between bits leaked is twice that shown in the table. x+07 7 r reserved: this bit must be set to zero. 6-4 exp. sig. label (2-0) expected signal label: bits 6 through 4 correspond to bits 5 through 7 respectively of v5 (gr-253-core issue 2, fig. 3-25) received from the telecom bus. the signal label mismatch detector compares these bits with those received from the telecom bus. set to 000 for unequipped, to 010 for asynchronous operation, to 001 for equipped non-specific, or to 100 for byte-synchronous operation. 3r reserved: this bit must be set to zero. 2-0 tx sig. label (2-0) transmit signal label: bits 2 through 0 correspond to bits 5 through 7 respectively of v5 (gr-253-core issue 2, fig. 3-25) to be sent out on the te l e c o m b u s . x+08 7 xpm external lais lead event mask: when set to one, this channel ? s lais events (xpe) are masked from generating interrupts (status and event not affected). 6dmpm demap error event mask: when set to one, this channel ? s demap error events (dmpe) are masked from generating interrupts (status and event not affected). 5losm los event mask: when set to one, this channel ? s los events (lose) are masked from generating interrupts (status and event not affected). 4mpm map error event mask: when set to one, this channel ? s map error events (mpe) are masked from generating interrupts (status and event not affected). 3daism ds1 ais event mask: when set to one, this channel ? s ds1 ais events (daise) are masked from generating interrupts (status and event not affected). address* bit symbol description pl8 - pl1 time between bits leaked from pointer leak buffer 00h 8 ms 01h 16 ms 02h 24 ms fdh 2,032 ms feh 2,040 ms ffh 2,048 ms - 126 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+08 (cont.) 2rpom received pointer justification counter overflow event mask: when set to one, received pointer justification counter overflow events (rpoe) from this channel are masked from generating interrupts (status and event not affected). 1 pgom generated pointer justification counter overflow event mask: when set to one, this channel ? s generated pointer justification counter overflow events (pgoe) are masked from generating interrupts (status and event not affected). 0cvom code violation counter/crc-6 error counter overflow event mask: when set to one, this channel ? s code violation counter/crc-6 error counter overflow events (cvoe) are masked from generating interrupts (status and event not affected). x+09 7 feom rei (febe) counter overflow event mask: when set to one, this chan- nel ? s rei (febe) counter overflow events (feoe) are masked from gener- ating interrupts (status and event not affected). 6bipom bip-2 error counter overflow event mask: when set to one, this chan- nel ? s bip-2 error counter overflow events (bipoe) are masked from gener- ating interrupts (status and event not affected). 5vaism vt ais event mask: when set to one, this channel ? s vt ais events (vaise) are masked from generating interrupts (status and event not affected). 4lopm loss of pointer event mask: when set to one, this channel ? s lop events (lope) are masked from generating interrupts (status and event not affected). 3rfim rfi event mask: when set to one, this channel ? s rfi events (rfie) are masked from generating interrupts (status and event not affected). 2unem unequipped event mask: when set to one, this channel ? s unequipped events (unee) are masked from generating interrupts (status and event not affected). set to one when this channel is programmed unequipped. 1slmm signal label mismatch event mask: when set to one, this channel ? s sig- nal label mismatch events (slme) are masked from generating interrupts (status and event not affected). set to one when this channel is pro- grammed unequipped. 0 rdim rdi event mask: when set to one, this channel ? s rdi events (rdi_ve) are masked from generating interrupts (status and event not affected). address* bit symbol description - 127 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+0a 7-3 r reserved: these bits must be set to zeros. 2 rdi-vpdm rdi-vpd event mask: when set to one, this channels ? s rdi-vpd events (rdi-vpde) are masked from generating interrupts (status and event not affected). 1 rdi-vsdm rdi-vsd event mask: when set to one, this channels ? s rdi-vsd events (rdi-vsde) are masked from generating interrupts (status and event not affected). 0 rdi-vcdm rdi-vcd event mask: when set to one, this channels ? s rdi-vcd events (rdi-vcde) are masked from generating interrupts (status and event not affected). x+0b 7-5 r reserved: these bits must be set to zeros. 4ringen ring port enable: when set to one, the outgoing v5 rei (febe) and rdi- vxx values are accepted from the ring port input. see rdiis and febeis above for logic. information input at the ring port is readable by the micro- processor in register x+3ah. 3-0 r reserved: these bits must be set to zeros. x+0c 7 dtlpbk ds1 tributary loopback: when set to one, the output of the coder is looped to the input of the decoder. clock, multiframe synchronization and signaling are also looped back. the ds1 tributary loopback can only be used in the asynchronous and modified byte-synchronous modes. this loopback is useful for t1mx28 self test with the prbs generator and ana- lyzer. 6dflpbk ds1 remote facility loopback: when set to one, the output of the decoder is looped to the input of the coder. clock, multiframe synchroniza- tion and signaling are also looped back. this loopback is used to provide remote facility loopback testing. 5rstch reset channel: when this bit is set to one, this channel is held in reset; it provides the same function that the resetp register (005h) provides for all channels. 4 sprbs send prbs: when set to one, the output of the prbs generator is substi- tuted for the output of the decoder for this channel. this bit, used in con- junction with dtlpbk (ds1 facility loopback), bit 7 in this register, tblpbkp (telecom bus loopback) at register 01eh bit 7, eprbsap (enable prbs generator/analyzer) at register 01ah bit 5, which must be set to one, and the ds1 channel number, provides a self test of this chan- nel. 3-0 r reserved: these bits must be set to zeros. x+0d - x+0f 7-0 r reserved: these registers should not be accessed. address* bit symbol description - 128 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers per channel status registers address* bit symbol description x+10 7 xps external lead status: when this bit is a one, the external lead (lais) for this channel is active per rxnrzpp (lais is high if rxnrzpp is zero or lais is low if rxnrzpp is one). 6dmps demap error status: when this bit is a one, a fault (e.g. internal fifo overflow/underflow) is occurring in the desynchronizer for this channel. 5loss loss of signal status: when this bit is a one, los is currently being detected in this channel. detection of los is based on no pulses being a logic low on both the rposn and rnegn leads for 175 75 contiguous clock cycles of lrclkn. los exits on 12.5% or greater ones density for 175 75 contiguous pulse positions. los does not function in nrz mode. 4mps map error status: when this bit is a one, a map error is occurring in this channel. if bit lof2vais is one, this bit represents a loss of multiframe input in byte-synchronous operation. 3daiss ds1 ais status: when this bit is a one, ds1 ais is being detected in the line decoder for this channel. ds1 ais is declared if 99.9% ones are detected for between 3 and 75 milliseconds. ais exits on less than 99.9% all-ones for between 3 and 75 milliseconds. 2rpos received pointer justification counter overflow status: when this bit is a one, the received pointer justification counter for this channel has over- flowed. 1 pgos generated pointer justification counter overflow status: when this bit is a one, the generated pointer justification counter has overflowed for this channel. 0cvop code violation counter/crc-6 error counter overflow status: when this bit is a one, the code violation counter/crc-6 error counter for this channel has overflowed. x+11 7 feos rei (febe) counter overflow status: when this bit is a one, the rei (febe) counter for this channel has overflowed. 6bipos bip-2 error counter overflow status: when this bit is a one, the bip-2 error counter for this channel has overflowed. 5vaiss vt ais status: when this bit is a one, vt ais is currently being detected for this channel. vt ais is declared if 3 consecutive v1 and v2 bytes are all-ones. vt ais is removed when a valid vt pointer is received with valid ss-bits, with a ndf, or with 3 consecutive vt superframes having a valid vt pointer and valid ss-bits with no ndf. 4lops lop status: when this bit is a one, loss of pointer is currently being detected for this channel. lop is entered with 8 consecutive ndf enables or invalid pointers. lop is exited to normal if 3 consecutive valid vt point- ers are received with valid ss-bits. lop is exited to ais if 3 consecutive all- ones pointers are received. - 129 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+11 (cont.) 3rfis rfi status: when this bit is a one, the receive failure indication has been de-bounced for 10 consecutive v5 bytes and is set for this channel. rfi is only a valid indication in byte-synchronous modes of operation. this bit will clear if rfi is reset in 10 consecutive v5 bytes. 2 unes unequipped status: this bit reflects the current status of the receive sig- nal label for this channel (de-bounced for 5 consecutive v5 bytes) with respect to unequipped (signal label = 000). when this bit is a one, the incoming vt1.5 or tu-11 is unequipped. this bit will clear if 5 consecutive v5 bytes do not have an all-zero signal label. 1slms signal label mismatch status: when this bit is set to a one, a mismatch has been de-bounced and detected for 5 consecutive v5 bytes between the expected signal label and the received signal label for this channel. a received or expected value of ? equipped non-specific ? (signal label = 001) is not a mismatch for any non-zero signal label. this bit will clear if 5 consec- utive v5 bytes match. an unequipped signal label (signal label = 000) received will cause this bit to be set unless the expected signal label (bits 6-4 of register x+07h) is set to unequipped. 0 rdi-vs rdi-v status: when this bit is a one, a remote defect indication (from equipment that does not support enhanced rdi) has been de-bounced for 5 or 10 consecutive v5 bytes and detected for this channel. this bit will clear if rdi is reset for 5 or 10 consecutive v5 bytes. rdid10p selects the de-bounce period. x+12 7-3 r reserved: these bits have indeterminate status on read. 2 rdi-vpds rdi-vpd status: when this bit is set to one, a vt remote payload defect indication has been de-bounced for 5 or 10 consecutive z7/k4 bytes and detected for this channel. this bit will clear if rdi-vpd is not received for 5 or 10 consecutive z7/k4 bytes. rdid10p selects the de-bounce period. 1 rdi-vsds rdi-vsd status: when this bit is set to one, a vt remote server defect indication has been de-bounced for 5 or 10 consecutive z7/k4 bytes and detected for this channel. this bit will clear if rdi-vsd is not received for 5 or 10 consecutive z7/k4 bytes. rdid10p selects the de-bounce period. 0 rdi-vcds rdi-vcd status: when this bit is set to one, a vt remote connectivity defect indication has been de-bounced for 5 or 10 consecutive z7/k4 bytes and detected for this channel. this bit will clear if rdi-vcd is not received for 5 or 10 consecutive z7/k4 bytes. rdid10p selects the de- bounce period. x+13 7-0 spare spare: this register should not be accessed. address* bit symbol description - 130 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+14 7 xpe external lead event: this bit will be set to one, when the active edge of the external lead (lais) for this channel (xps), as determined by risep and fallp, and the sense as determined by rxnrzpp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpm- fmp is set to one. 6dmpe demap error event: this bit will be set to one, when the active edge of a demap error for this channel (dmps), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 5lose loss of signal event: this bit will be set to one, when the active edge of an los for this channel (loss), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 4mpe map error event: this bit will be set to one, when the active edge of a map error for this channel (mps), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 3daise ds1 ais event: this bit will be set to one, when the active edge of a ds1 ais for this channel (daiss), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 2rpoe received pointer justification counter overflow event: this bit will be set to one, when the active edge of a received pointer justification counter overflow for this channel (rpos), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 1 pgoe generated pointer justification counter overflow event: this bit will be set to one, when the active edge of a generated pointer justification counter overflow for this channel (pgos), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 0cvoe code violation counter/crc-6 error counter overflow event: this bit will be set to one, when the active edge of a code violation counter/crc-6 error counter overflow for this channel (cvos), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. address* bit symbol description - 131 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+15 7 feoe rei (febe) counter overflow event: this bit will be set to one, when the active edge of a rei (febe) counter overflow for this channel (feos), as determined by risep and fallp, has occurred. this bit is cleared by writ- ing a zero to this bit location or by t1si if enpmfmp is set to one. 6bipoe bip-2 error counter overflow event: this bit will be set to one, when the active edge of a bip-2 error counter overflow for this channel (bipos), as determined by risep and fallp, has occurred. this bit is cleared by writ- ing a zero to this bit location or by t1si if enpmfmp is set to one. 5vaise vt ais event: this bit will be set to one, when the active edge of a vt ais for this channel (vaiss), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 4lope lop event: this bit will be set to one, when the active edge of a lop for this channel (lops), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpm- fmp is set to one. 3rfie rfi event: this bit will be set to one, when the active edge of an rfi for this channel (rfis), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 2 unee unequipped event: this bit will be set to one, when the active edge of an unequipped signal label for this channel (unes), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 1slme signal label mismatch event: this bit will be set to one, when the active edge of a signal label mismatch for this channel (slms), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 0 rdi-ve rdi-v event: this bit will be set to one, when the active edge of an rdi for this channel (rdi-vs), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. x+16 7-3 r reserved: these bits must be set to zeros. 2 rdi-vpde rdi-vpd event: this bit will be set to one, when the active edge of an rdi-vpd for this channel (rdi-vpds), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 1 rdi-vsde rdi-vsd event: this bit will be set to one, when the active edge of an rdi-vsd for this channel (rdi-vsds), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. 0 rdi-vcde rdi-vcd event: this bit will be set to one, when the active edge of an rdi-vcd for this channel (rdi-vcds), as determined by risep and fallp, has occurred. this bit is cleared by writing a zero to this bit location or by t1si if enpmfmp is set to one. address* bit symbol description - 132 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+17 7-0 spare spare: this register should not be accessed. x+18 7 xppm external lead performance monitor: this bit will be set to one, if an external lead event (xpe) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writ- ing it to a zero. 6dmppm demap error performance monitor: this bit will be set to one, if a demap error event (dmpe) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 5lospm loss of signal performance monitor: this bit will be set to one, if an los event (lose) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 4mppm map error performance monitor: this bit will be set to one, if a map error event (mpe) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 3 daispm ds1 ais performance monitor: this bit will be set to one, if a ds1 ais event (daise) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 2rpopm received pointer justification counter overflow performance moni- tor: this bit will be set to one, if a received pointer justification counter overflow event (rpoe) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writ- ing it to a zero. 1 pgopm generated pointer justification counter overflow performance moni- tor: this bit will be set to one, if a generated pointer justification counter overflow event (pgoe) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writ- ing it to a zero. 0cvopm code violation counter/crc-6 error counter overflow performance monitor: this bit will be set to one, if a code violation counter/crc-6 error counter overflow event (cvoe) has occurred in the last one-second inter- val as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. address* bit symbol description - 133 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+19 7 feopm rei (febe) counter overflow performance monitor: this bit will be set to one, if a rei (febe) counter overflow event (feoe) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 6bipopm bip-2 error counter overflow performance monitor: this bit will be set to one, if a bip-2 counter overflow event (bipoe) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 5vaispm vt ais performance monitor: this bit will be set to one, if a vt ais event (vaise) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 4loppm lop performance monitor: this bit will be set to one, if an lop event (lope) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 3rfipm rfi performance monitor: this bit will be set to one, if an rfi event (rfie) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 2unepm unequipped performance monitor: this bit will be set to one, if an unequipped signal label event (unee) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 1slmpm signal label mismatch performance monitor: this bit will be set to one, if a signal label mismatch event (slme) has occurred in the last one-sec- ond interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 0 rdi-vpm rdi-v performance monitor: this bit will be set to one, if an rdi event (rdi-ve) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. x+1a 7-3 r reserved: these bits must be set to zeros. 2 rdi-vpdpm rdi-vpd performance monitor: this bit will be set to one, if an rdi-vpd event (rdi-vpde) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 1 rdi-vsdpm rdi-vsd performance monitor: this bit will be set to one, if an rdi-vsd event (rdi-vsde) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 0 rdi-vcdpm rdi-vcd performance monitor: this bit will be set to one, if an rdi-vcd event (rdi-vcde) has occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. x+1b 7-0 spare spare: this register should not be accessed. address* bit symbol description - 134 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+1c 7 xpfm external lead fault monitor: this bit will be set to one, if an external lead event (xpe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 6dmpfm demap error fault monitor: this bit will be set to one, if a demap error event (dmpe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 5losfm loss of signal fault monitor: this bit will be set to one, if an los event (lose) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 4mpfm map error fault monitor: this bit will be set to one, if a map error event (mpe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 3daisfm ds1 ais fault monitor: this bit will be set to one, if a ds1 ais event (daise) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 2rpofm received pointer justification counter overflow fault monitor: this bit will be set to one, if a received pointer justification counter overflow event (rpoe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 1pgofm generated pointer justification counter overflow fault monitor: this bit will be set to one, if a generated pointer justification counter overflow event (pgoe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 0cvofm code violation counter/crc-6 error counter overflow fault monitor: this bit will be set to one, if a code violation counter/crc-6 error counter overflow event (cvoe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. address* bit symbol description - 135 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+1d 7 feofm rei (febe) counter overflow fault monitor: this bit will be set to one, if a rei (febe) counter overflow event (feoe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 6bipofm bip-2 error counter overflow fault monitor: this bit will be set to one, if a bip-2 error counter overflow event (bipoe) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 5 vaisfm vt ais fault monitor: this bit will be set to one, if a vt ais event (vaise) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 4lopfm lop fault monitor: this bit will be set to one, if a lop event (lope) is active but the transition to the active state has not occurred in the last one- second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 3 rfifm rfi fault monitor: this bit will be set to one, if an rfi event (rfie) is active but the transition to the active state has not occurred in the last one- second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 2 unefm unequipped fault monitor: this bit will be set to one, if an unequipped signal label event (unee) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 1slmfm signal label mismatch fault monitor: this bit will be set to one, if a sig- nal label mismatch event (slme) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 0 rdi-vfm rdi-v fault monitor: this bit will be set to one, if an rdi event (rdi-ve) is active but the transition to the active state has not occurred in the last one- second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. x+1e 7-3 reserved reserved: these bits must be set to zeros. 2 rdi-vpdfm rdi-vpd fault monitor: this bit will be set to one, if an rdi-vpd event (rdi-vpde) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. 1 rdi-vsdfm rdi-vsd fault monitor: this bit will be set to one, if an rdi-vsd event (rdi-vsde) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. address* bit symbol description - 136 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+1e (cont.) 0 rdi-vcdfm rdi-vcd fault monitor: this bit will be set to one, if an rdi-vcd event (rdi-vcde) is active but the transition to the active state has not occurred in the last one-second interval as defined by t1si, if enpmfmp is set to one. this bit may be cleared by writing it to a zero. x+1f 7-0 spare spare: this register should not be accessed. x+20 7 shdais signaling highway ds1 ais status: this bit is a one if a ds1 ais indica- tion is received from the signaling highway in byte-synchronous mode only. 6shyel signaling highway yellow: this bit is a one if a ds1 yellow indication is received from the signaling highway in byte-synchronous mode only. 5r reserved: this bit reads out as zero. 4, 3 rxss1, rxss0 received ss-bits: these two bits represent the ss-bits (ss-bit 1 and ss- bit 0 respectively) received from the vt1.5 or tu-11 v1 and v2 bytes. 2-0 rx signal label (2-0) receive signal label: these bits represent the signal label received from the v5 byte for this channel. bits 2 through 0 correspond to bits 5 through 7 respectively of the v5 byte received from the telecom bus. x+21 7-0 spare spare: this register should not be accessed. x+22 7-0 cvc7-cvc0 line code violation counter/crc-6 error counter: this is the lower byte of a 12-bit free running counter which will increment by one for each received line code violation. if excessive zeros counting is enabled (enzc is set to one) they will also be counted with the line code errors. this counter can be cleared by writing its value to zero. if the counter overflows the cvos and cvoe bits (plus cvopm and cvofm bits if enpmfmp is set) will be set. if enpmfmp is set, this counter ? s latched value is updated every one-second at lcvc7-lcvc0 and this counter is subsequently cleared for the next one-second interval. when crc-6 (x+01h, bit 4) is set, this counter is used as the crc-6 error counter lower byte in byte-syn- chronous modes only. x+23 7-4 r reserved: these bits must be set to zeros. 3-0 cvc11- cvc8 line code violation counter/crc-6 error counter: this is the upper nibble of a 12-bit free running counter which will increment by one for each received line code violation. if excessive zeros counting is enabled (enzc is set to one) they will also be counted with the line code errors. this counter can be cleared by writing its value to zero. if the counter overflows the cvos and cvoe bits (plus cvopm and cvofm bits if enpmfmp is set) will be set. if enpmfmp is set, this counter ? s latched value is updated every one-second at lcvc11-lcvc8 and this counter is subsequently cleared for the next one-second interval. when crc-6 (x+01h, bit 4) is set, this counter is used as crc-6 error counter upper nibble in byte-syn- chronous modes only. address* bit symbol description - 137 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+24 7-4 rx ptr. inc. counter pointer increments received counter: this four-bit counter represents the number of vt pointer increments received for this channel. this counter can be cleared by writing its value to zero. if the counter overflows the rpos and rpoe bits (plus rpopm and rpofm bits if enpmfmp is set) will be set. if enpmfmp is set, this counter ? s latched value is updated every one-second at address x+23h and this counter is subsequently cleared for the next one-second interval. 3-0 rx ptr. dec. counter pointer decrements received counter: this four-bit counter represents the number of vt pointer decrements received for this channel. this counter can be cleared by writing its value to zero. if the counter overflows the rpos and rpoe bits (plus rpopm and rpofm bits if enpmfmp is set) will be set. if enpmfmp is set, this counter ? s latched value is updated every one-second at address x+23h and this counter is subsequently cleared for the next one-second interval. x+25 7-4 ptr. inc. gen. counter pointer increments generated counter: this four-bit counter represents the number of vt pointer increments generated by this channel for byte- synchronous mode of operation. this counter can be cleared by writing its value to zero. if the counter overflows the pgos and pgoe bits (plus pgopm and pgofm bits if enpmfmp is set) will be set. if enpmfmp is set, this counter ? s latched value is updated every one-second at address x+24h and this counter is subsequently cleared for the next one-second interval. 3-0 ptr dec. gen. counter pointer decrements generated counter: this four-bit counter repre- sents the number of vt pointer decrements received for this channel. this counter can be cleared by writing its value to zero. if the counter overflows the pgos and pgoe bits (plus pgopm and pgofm bits if enpmfmp is set) will be set. if enpmfmp is set, this counter ? s latched value is updated every one-second at address x+24h and this counter is subsequently cleared for the next one-second interval. x+26 7-0 bec7-bec0 bip-2 error counter: this is the lower byte of a 12-bit free running counter. when control bit sdhp is set to zero, it will increment by one for each bip-2 error received. when sdhp is set to one, it will increment block counts of bip-2 errors. this counter can be cleared by writing its value to zero. if the counter overflows the bipos and bipoe bits (plus bipopm and bipofm bits if enpmfmp is set) will be set. if enpmfmp is set, this counter ? s latched value is updated every one-second at lbec7-lbec0 and this counter is subsequently cleared for the next one-second interval. x+27 7-4 r reserved: these bits must be set to zeros. 3-0 bec11- bec8 bip-2 error counter: this is the upper nibble of a 12-bit free running counter. when control sdhp is set to zero, it will increment by one for each bip-2 error received. when sdhp is set to one, it will increment block counts of bip-2 errors. this counter can be cleared by writing its value to zero. if the counter overflows the bipos and bipoe bits (plus bipopm and bipofm bits if enpmfmp is set) will be set. if enpmfmp is set, this counter ? s latched value is updated every one-second at lbec11-lbec8 and this counter is subsequently cleared for the next one-second interval. address* bit symbol description - 138 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+28 7-0 fec7-fec0 rei (febe) counter: this is the lower byte of a 12-bit free running counter which will increment by one for each far end block error received. this counter can be cleared by writing its value to zero. if the counter over- flows the feos and feoe bits (plus feopm and feofm bits if enpmfmp is set) will be set. if enpmfmp is set, this counter ? s latched value is updated every one-second at lfec7-lfec0 and this counter is subsequently cleared for the next one-second interval. x+29 7-4 r reserved: these bits must be set to zeros. 3-0 fec11- fec8 rei (febe) counter: this is the upper nibble of a 12-bit free running counter which will increment by one for each far end block error received. this counter can be cleared by writing its value to zero. if the counter over- flows the feos and feoe bits (plus feopm and feofm bits if enpmfmp is set) will be set. if enpmfmp is set, this counter ? s latched value is updated every one-second at lfec11-lfec8 and this counter is subsequently cleared for the next one-second interval. x+2a 7-0 lcvc7- lcvc0 latched line code violation counter/crc-6 error counter: this is the lower byte of a 12-bit shadow register which is updated from the line code violation counter once a second. the one-second interval is derived from the external one-second input, t1si. when crc6 (x+01h, bit 4) is set, this counter is used as crc-6 error counter lower byte in byte-synchronous modes only. x+2b 7-4 r reserved: these bits must be set to zeros. 3-0 lcvc11- lcvc8 latched line code violation counter/crc-6 error counter: this is the upper nibble of a 12-bit shadow register which is updated from the line code violation counter once a second. the one-second interval is derived from the external one-second input, t1si. when crc6 (x+01h, bit 4) is set, this counter is used as crc-6 error counter upper nibble in byte-syn- chronous modes only. x+2c 7-4 latched rx ptr. inc. counter latched pointer increments received counter: this is the 4-bit shadow register which is updated from the pointer increments received counter once a second. the one-second interval is derived from the external one- second input, t1si. 3-0 latched rx ptr. dec. counter latched pointer decrements received counter: this is the 4-bit shadow register which is updated from the pointer decrements received counter once a second. the one-second interval is derived from the exter- nal one-second input, t1si. x+2d 7-4 latched ptr. inc. gen. counter latched pointer increments generated counter: this is the 4-bit shadow register which is updated from the pointer increments generated counter once a second. the one-second interval is derived from the exter- nal one-second input, t1si. 3-0 latched ptr. dec. gen. counter latched pointer decrements generated counter: this is the 4-bit shadow register which is updated from the pointer decrements generated counter once a second. the one-second interval is derived from the exter- nal one-second input, t1si. address* bit symbol description - 139 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+2e 7-0 lbec7- lbec0 latched bip-2 error counter: this is the lower byte of a 12-bit shadow register which is updated from the bip-2 error counter once a second. the one-second interval is derived from the external one-second input, t1si. x+2f 7-4 r reserved: these bits must be set to zeros. 3-0 lbec11- lbec8 latched bip-2 error counter: this is the upper nibble of a 12-bit shadow register which is updated from the bip-2 error counter once a second. the one-second interval is derived from the external one-second input, t1si. x+30 7-0 lfec7- lfec0 latched rei (febe) counter: this is the lower byte of a 12-bit shadow register which is updated from the rei (febe) counter once a second. the one-second interval is derived from the external one-second input, t1si. x+31 7-4 r reserved: these bits must be set to zeros. 3-0 lfec11- lfec8 latched rei (febe) counter: this is the upper nibble of a 12-bit shadow register which is updated from the rei (febe) counter once a second. the one-second interval is derived from the external one-second input, t1si. x+32 7-0 rxob7- rxob0 received o-bits: bits 3, 2, 1 and 0 are the first four o-bits (byte following j2, bits 3, 4, 5 and 6) incoming on add(0-7) (for p = 1 and 2) or bdd(0-7) (for p = 3 and 4). the second four o-bits (byte following z6/n2, bits 3, 4, 5 and 6) are placed in bits 7, 6, 5 and 4. x+33 7-0 rxj27- rxj20 received j2 byte: bit 7 is bit 1 of the j2 byte incoming on add(0-7) (for p = 1 and 2) or bdd(0-7) (for p = 3 and 4). bit 0 is bit 8 of the j2 byte. x+34 7-0 rxz67- rxz60 received z6/n2 byte: bit 7 is bit 1 of the z6/n2 byte incoming on add(0-7) (for p = 1 and 2) or bdd(0-7) (for p = 3 and 4). bit 0 is bit 8 of the z6/n2 byte. x+35 7-0 rxz77- rxz70 received z7/k4 byte: bit 7 is bit 1 of the z7/k4 byte incoming on add(0-7) (for p = 1 and 2) or bdd(0-7) (for p = 3 and 4). bit 0 is bit 8 of the z7/k4 byte. x+36 7-0 txob7- txob0 transmit o-bits: bits 3, 2, 1 and 0 are the first four o-bits (byte following j2, bits 3, 4, 5 and 6). the second four o-bits (byte following z6/n2, bits 3, 4, 5 and 6) are bits 7, 6, 5 and 4. the microprocessor ? written data, in this location is output on aad(0-7) (for p = 1 and 2) or bad(0-7) (for p = 3 and 4). control bit tbtval (register x+05h bit 7) must be set to a "1" to be able to read this register after it is written. x+37 7-0 txj27- txj20 transmit j2 byte: bit 7 is bit 1 of the j2 byte and bit 0 is the bit 8 of the j2 byte. the microprocessor-written data in this location, is output on aad(0- 7) (for p = 1 and 2) or bad(0-7) (for p = 3 and 4). control bit tbtval (reg- ister x+05h bit 7) must be set to a "1" to be able to read this register after it is written. x+38 7-0 txz67- txz60 transmit z6/n2 byte: bit 7 is bit 1 of the z6/n2 byte and bit 0 is bit 8 of the z6/n2 byte. the microprocessor-written data, in this location, is output on aad(0-7) (for p = 1 and 2) or bad(0-7) (for p = 3 and 4). control bit tbtval (register x+05h bit 7) must be set to a "1" to be able to read this register after it is written. address* bit symbol description - 140 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers x+39 7-0 txz77- txz70 transmit z7/k4 byte: bit 7 is bit 1 of the z7/k4 byte and bit 0 is bit 8 of the z7/k4 byte. the microprocessor ? written data, in this location, is output on aad(0-7) (for p = 1 and 2) or bad(0-7) (for p = 3 and 4). only bits 7-4 and 0 will appear in the output. bits 1, 2 and 3 are controlled by the transmit rdi circuity. for proper idle operation this register should be set to 00h. control bit tbtval (register x+05h bit 7) must be set to a "1" to be able to read this register after it is written. x+3a 7-4 r reserved: these bits have indeterminate status on read. 3 rgfebe-v ring port rei (febe) input: this location contains the information input at the ring port. control bit ringen (bit 4) in register x+0bh must be set to a one. 2 rgrdi-vpd ring port path defect input: this location contains the information input at the ring port. control bit ringen (bit 4) in register x+0bh must be set to a one. 1 rgrdi-vsd ring port server defect input: this location contains the information input at the ring port. control bit ringen (bit 4) in register x+0bh must be set to a one. 0 rgrdi-vcd ring port connectivity defect input: this location contains the informa- tion input at the ring port. control bit ringen (bit 4) in register x+0bh must be set to a one. x+3b - x+3f 7-0 reserved reserved: these registers should not be accessed. address* bit symbol description - 141 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers application diagrams the t1mx28 can be used in a wide range of telecommunication and data communication applications: sonet or sdh add/drop multiplexer sonet or sdh terminal multiplexer remote digital terminal internet access equipment test and monitoring equipment for sonet or sdh applications figure 44. typical applications using the t1mx28 the application diagram in figure 44 shows four different uses for the t1mx28. for sonet byte-synchronous application the t1mx28 is connected to four t1fx8s and provides for mapping 28 ds1s byte-synchronously. liu control can be provided by either the t1fx8 or the t1mx28. direct ds0 access is available for byte- synchronous mappings (external slip buffers are required for common clocks across more than 24 ds0s). with the t1fx8, ds0 access is also available from ds1s mapped asynchronously. for asynchronous ds1 mappings, the t1mx28 can be connected directly to most commercial liu devices and control them; this example depicts the dual bus application. t1mx28 txc-04228 phast-3n txc-06103 sonet sts-3 t1mx28 txc-04228 t1mx28 txc-04228 t1mx28 txc-04228 t1fx8 txc-03108 liu 24 ds0+sig, clock & frame 24 ds0+sig, clock & frame 24 ds0+sig, clock & frame ds1(1) ds1(2) ds1(3) ds1(4) ds1(26) ds1(27) ds1(28) ds1(1) ds1(14) (async) (byte sync) (async) t1fx8 txc-03108 (byte sync) t1fx8 txc-03108 octal liu octal liu phast-3n txc-06103 sonet sts-3 1 4 1 4 x 28 1 4 liu note: additional components, including level converters, may be required in some applications. t1mx28 txc-04228 phast-3n txc-06103 sonet sts-3 t1mx28 txc-04228 t1mx28 txc-04228 t1mx28 txc-04228 t1fx8 txc-03108 liu 24 ds0+sig, clock & frame 24 ds0+sig, clock & frame 24 ds0+sig, clock & frame ds1(1) ds1(2) ds1(3) ds1(4) ds1(26) ds1(27) ds1(28) ds1(1) ds1(14) (async) (byte sync) (async) t1fx8 txc-03108 (byte sync) t1fx8 txc-03108 octal liu octal liu phast-3n txc-06103 sonet sts-3 1 4 1 4 x 28 1 4 liu note: additional components, including level converters, may be required in some applications. - 142 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers package information the t1mx28 device is packaged in a 456-lead plastic ball grid array package suitable for surface mounting, as illustrated in figure 45. figure 45. t1mx28 txc-04228 456-lead plastic ball grid array package dimension (note 1) min max a 2.12 2.72 notes: 1. all dimensions are in millimeters. values shown are for reference only. 2. identification of the solder ball a1 corner is contained within this shaded zone. package corner may not be a 90 angle. a1 0.50 0.70 a2 (nom) 1.17 a3 (nom) 0.65 b (ref.) 0.76 d 34.90 35.10 d1 (nom) 31.75 d2 33.60 33.80 e 34.90 35.10 e1 (nom) 31.75 e2 33.60 33.80 e (ref.) 1.27 a rpnm kjhgfedcb 1 2 3 4 5 6 7 8 9 11 12 13 14 15 b e d d2 note 2 e1/4 d1/4 -d1- a2 a3 a a1 bottom view transwitch txc-04228aibg t 16 l 17 18 19 20 21 23 22 u ac ab aa y w v 10 e e2 -e1- ae ad af 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 58 51 24 25 26 58 51 58 51 58 51 58 51 - 143 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers ordering information part number: txc-04228aibg 456-lead plastic ball grid array package related products txc-02020, art vlsi device (advanced sts-1/ds3 receiver/transmitter). art performs the transmit and receive line interface functions required for transmission of sts-1 (51.840 mbit/s) and ds3 (44.736 mbit/s) signals across a coaxial interface. txc-02021, arte vlsi device (advanced sts-1/ds3 receiver/transmitter). arte has the same functionality as art, plus extended features. txc-02302b, syn155c vlsi device (155-mbit/s synchronizer, clock and data output). this device provides a complete sts-3/stm-1 frame synchronization function in a single cmos unit. txc-03001b, sot-1 vlsi device (sonet sts-1 overhead terminator). performs section, line, and path overhead processing for sts-1 sonet signals. interfaces are provided for both section and line orderwire and datacom channels. further, control bits in the memory map enable the sot-1 to perform loopback and serial or parallel i/o. txc-03003b, sot-3 vlsi device (stm-1/sts-3/sts-3c overhead terminator). this is a pro- grammable device that performs section, line and path overhead processing for stm-1/sts-3/ sts-3c signals. the sot-3 device performs pointer generation (with internal pointer justifica- tion) with respect to external clock timing in both the transmit and receive directions. txc-03011, sot-1e vlsi device (sonet sts-1 overhead terminator). this device provides extended features relative to the 84-lead txc-03001 and txc-03001b sot-1 devices, and it has a 144-lead package. txc-03108, t1fx8 vlsi device (8-channel t1 framer). an 8-channel framer for voice and data communications applications. this device handles all logical interfacing functionality to a t1 line and operates from a power supply of 3.3 volts. txc-04201b, ds1mx7 vlsi device (ds1 mapper 7-channel). maps seven 1.544 mbit/s ds1 signals into any seven selected asynchronous or byte-synchronous mode vt1.5 or tu-11 vir- tual tributaries carried in a sonet or sdh synchronous payload envelope. txc-04251, qt1m vlsi device (quad ds1 to vt1.5 or tu-11 async mapper-desync). inter- connects four ds1 signals with any four asynchronous mode vt1.5 or tu-11 tributaries car- ried in sonet sts-1 or sdh au-3 rate payload interface. txc-06101, phast-1 vlsi device (sonet sts-1 overhead terminator). this device pro- vides features similar to those of the txc-03011 sot-1e device, but it operates from a power supply of 3.3 volts rather than 5 volts. txc-06103, phast-3n vlsi device (sonet stm-1, sts-3 or sts-3c overhead terminator). this phast-3n vlsi device provides a telecom bus interface for downstream devices. it operates from a power supply of 3.3 volts. - 144 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: (212) 642-4900 11 west 42nd street fax: (212) 302-1286 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 2570 west el camino real tel: (650) 949-6700 suite 304 fax: (650) 949-6705 mountain view, ca 94040 web: www.atmforum.com atm forum europe office av. de tervueren 402 tel: 2 761 66 77 1150 brussels fax: 2 761 66 79 belgium atm forum asia-pacific office hamamatsu-cho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsu-cho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan bellcore (see telcordia) ccitt ( see itu-t) eia (u.s.a.): electronic industries association tel: (800) 854-7179 (within u.s.a.) global engineering documents tel: (314) 726-0444 (outside u.s.a.) 7730 carondelet avenue, suite 407 fax: (314) 726-6418 clayton, mo 63105-3329 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 22 650 route des lucioles fax: 4 92 94 43 33 06921 sophia antipolis cedex web: www.etsi.org france - 145 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: (800) 669-6857 (within u.s.a.) tel: (903) 769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: (508) 650-1375 washington, dc 20007 web: www.mvip.org itu-t (international): publication services of international telecommunication union tel: 22 730 5111 telecommunication standardization sector fax: 22 733 7256 place des nations, ch 1211 web: www.itu.int geneve 20, switzerland mil-std (u.s.a.): dodssp standardization documents ordering desk tel: (215) 697-2179 building 4 / section d fax: (215) 697-1462 700 robbins avenue web: www.dodssp.daps.mil philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: (800) 433-5177 (within u.s.a.) 2575 ne kathryn street #17 tel: (503) 693-6232 (outside u.s.a.) hillsboro, or 97124 fax: (503) 693-8344 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: (800) 521-core (within u.s.a.) attention - customer service tel: (908) 699-5800 (outside u.s.a.) 8 corporate place fax: (908) 336-2559 piscataway, nj 08854 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunications technology committee tel: 3 3432 1551 fax: 3 3432 1553 2nd floor, hamamatsu-cho suzuki building, web: www.ttc.or.jp 1 2-11, hamamatsu-cho, minato-ku, tokyo - 146 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers list of data sheet changes this change list identifies those areas within this updated t1mx28 data sheet that have significant differences relative to the previous and now superseded t1mx28 data sheet: updated t1mx28 data sheet: preliminary ed. 4, september 2001 previous t1mx28 data sheet: preliminary ed. 3, april 2001. the page numbers indicated below of this updated data sheet include changes relative to the previous data sheet. page number of updated data sheet summary of the change all changed edition number and date. 25 for the symbols aaadd(1-2) and baadd(1-2) , removed the tristate (t) designation from the i/o/p column and changed the last sentence in the name/function column. 37 changed the min times for t h(1) , t h(2) , and t h(3) in figure 8 to 6.0 ns. 38 changed the min times for t h(1 ), t h(2) , and t h(3) in figure 9 to 6.0 ns. 47 added t h(2) to the timing diagram and table in figure 17 for addr (0-8). 143 deleted last entry under related products (txc-06112). 146 replaced ? list of data sheet changes ? section. - 147 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers - notes - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. preliminary information documents con- tain information on products in the sampling, preproduction or early production phases of the product life cycle. characteristic data and other specifications are subject to change. contact transwitch applications engineering for current information on this product. - 148 of 150 - transwitch corporation ? 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 - 149 of 150 - preliminary txc-04228-mb ed. 4, september 2001 t1mx28 txc-04228 data sheet proprietary transwitch corporation information for use solely by its customers documentation update registration form if you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the marketing communications department at transwitch. marketing communications will ensure that the relevant product information sheets, data sheets, application notes, technical bulletins and other publications are sent to you. you may also choose to provide the same information by fax (203.926.9453) , or by e-mail (info@txc.com) , or by telephone (203.929.8810) . most of these documents will also be made immediately available for direct download as adobe pdf files from the transwitch world wide web site ( www.transwitch.com ). name: _________________________________________________________________________________ company: __________________________________________ title: ______________________________ dept./mailstop: __________________________________________________________________________ street: _________________________________________________________________________________ city/state/zip: ___________________________________________________________________________ if located outside u.s.a., please add - country: ________________ postal code: ____________________ telephone: _______________________ ext.: ____________ fax: __________________________ e-mail: _______________________________________________ please provide the following details for the managers in charge of the following departments at your company location. department title name company/division __________________ __________________ engineering __________________ __________________ marketing __________________ __________________ please describe briefly your intended application(s) and indicate whether you would like to have a transwitch applications engineer contact you to provide further assistance: ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ please fold, tape and mail this page (see other side) or fax it to marketing communications at 203.926.9453. transwitch corporation attention: marketing communications dept. 3 enterprise drive shelton, ct 06484-4694 u.s.a. first class postage required please complete the registration form on this back cover sheet, and mail or fax it, if you wish to receive updated documentation on selected transwitch products as it becomes available. (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 3 enterprise drive shelton, ct 06484-4694 u.s.a. |
Price & Availability of TXC04228
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |